Triple data rate would be quite awkward. DDR and QDR configure logically around the rising and falling of the clock signal; QDR uses separate data buses for read and write. At last check, QDR was absurdly expensive, making it unsuitable for consumer applications.DDR 2 DDR 3 DDR 4 DDR 5 .. why arent we going TDR or QDR ? been using DDR technology long time already
The only thing QDR does is reduce the amount of power needed to drive the bus clock at the expense of extra circuitry in the GDDR5+ chips to internally generate the extra edges for the QDR IOs.DDR 2 DDR 3 DDR 4 DDR 5 .. why arent we going TDR or QDR ? been using DDR technology long time already
No, QDR only means nothing more than the data rate is 4X the clock frequency. Even GDDR6X with its new PAM4 signaling still shares IO pins between reads and writes. What "got split" with GDDR6 is that the chips are internally structured as two independent 16bits-wide banks, so you can configure them as either 1x32bits or 2x16bits.QDR uses separate data buses for read and write.
You equated QDR to having separate DDR R/W ports. Those two things are completely unrelated, GDDR5/5X/6/6X all have single QDR data ports.Hmm, what's the source of my confusion then? I'm unsure now.
Nothing special about it, DDR4 DIMMs are available in 18GB and 36GB sizes due to ECC.18GB is a rather odd amount of memory.
Looking around for ECC DDR4 RAM modules, they advertise their usable memory size, not total memory size.Nothing special about it, DDR4 DIMMs are available in 18GB and 36GB sizes due to ECC.
Not really. This announcement is about DRAM packages and bare chips have pretty much always been marketed based on raw specs. The only difference here is that prior to DDR5, ECC was optional and was implemented by including the extra DRAM package(s) for ECC bits.Looks like someone in marketing convinced the higher ups to drink the numbers koolaid.
Except CPU speed, core count and all that other stuff has little to do with what ECC helps the most with in the context of DRAM.Computer speeds/threads ever increasing means those cosmic rays (or some such) have a higher probability of flipping a single bit (or more)).