News SMIC and Huawei could use quadruple patterning for China-made 5nm chips: Report

[Admin]

Something that almost killed Intel is now patented in China. But it remains to be seen how viable it will be.

SMIC and Huawei could use quadruple patterning for China-made 5nm chips: Report : Read more

 

[jkflipflop98]

It's going to happen, eventually. The chinese aren't stupid, and they have the full backing of a nation's resources behind them. Eventually they're going to home-brew their own solution to this problem.

 

[The Historical Fidelity]

It's going to happen, eventually. The chinese aren't stupid, and they have the full backing of a nation's resources behind them. Eventually they're going to home-brew their own solution to this problem.

Yes but the real question is will they be able to develop EUV while it is still relevant. The west is already well underway developing BEUV and soft X-Ray lithography.

 

[jkflipflop98]

That's very true. It could be EUV, it may be some type of electron beam based solution, it may be something totally radical no one else has ever thought of.

 

[The Historical Fidelity]

That's very true. It could be EUV, it may be some type of electron beam based solution, it may be something totally radical no one else has ever thought of.

Very true, and the west could obsolete all of China’s development by coming out with some radical new lithography. But let’s not swim in theoreticals. Most likely China will need 20 to 30 years to develop EUV, then create the on-shore infrastructure to replace their former access to the global lithography supply ecosystem. This assumes China does not cheat by hacking or spying of course.

 

[Pierce2623]

It's going to happen, eventually. The chinese aren't stupid, and they have the full backing of a nation's resources behind them. Eventually they're going to home-brew their own solution to this problem.

Oh sure, everything happens eventually. Right now though, this stuff is meaningless. Their “7nm” was already extremely far behind on performance compared to TSMC 7nm, and the same will apply to “5nm” as well. Also trying to stretch old technology way beyond it’s effective ceiling also makes these extremely expensive nodes to use as well.

 

[usertests]

It's going to happen, eventually. The chinese aren't stupid, and they have the full backing of a nation's resources behind them. Eventually they're going to home-brew their own solution to this problem.

It would be funny if they offered cheaper chips even with the quadruple patterning. But if the application demands homegrown solutions, they can eat the cost, and some products are so expensive that the wafer costs don't even matter.

For example, Wafer Scale Engine units are apparently sold for millions of dollars but TSMC N5 wafers cost only $16,000. Consumer electronics may suffer from high wafer costs but enterprise-grade AI chips are the thing that's in short supply right now. Many home and office PCs would be fine with e.g. a 28/22/14nm class node. The latest 8-core Zhaoxin x86 CPUs of unknown fab origin are overkill for personal computing and apparently not affected by sanctions yet, so they should try to get as many of those as they can.

Even if the latest SMIC process node is more expensive, less performant, and less efficient than the competition, it can be fine because the most important thing right now is volume (especially having more than... zero wafers). They can catch up later, which will be easier to do if transistor progress is slow or halted.

 

[edzieba]

The very same method was a major reason for the failure of Intel’s 1st Generation 10nm-class process technology

But also worked perfectly well for all subsequent 10nm-class processes, including those used to fab their desktop chips today. SAQP does not appear to have been a limiter for yields or output volume.

 

[Chips4all]

Oh sure, everything happens eventually. Right now though, this stuff is meaningless. Their “7nm” was already extremely far behind on performance compared to TSMC 7nm, and the same will apply to “5nm” as well. Also trying to stretch old technology way beyond it’s effective ceiling also makes these extremely expensive nodes to use as well.

The next challenge will be economic, that is political, with 19 fabs coming online to dump/corner the >17nm chip market & leverage such capacity in the >5nm production, despite throughput, yields, even binnings, being at such low levels they would bankrupt any Western company vs state-owned or subsidized Chinese sector.
What products need such chip production capacity is obviously cars or military. --- time to do more work in the West & focus on US STEM here.

 

[Chips4all]

But also worked perfectly well for all subsequent 10nm-class processes, including those used to fab their desktop chips today. SAQP does not appear to have been a limiter for yields or output volume.

Definitely there was an increased cost for multiple litho lines, storage & amhs, but once in place the constraint tool issue was no longer & target throughput ok.... Yield/binning issues can be addressed.

 

[COLGeek]

Folks, as a reminder. Focus on the technology aspect of the topic. Not politics. Thank you.

 

[edzieba]

Definitely there was an increased cost for multiple litho lines, storage & amhs, but once in place the constraint tool issue was no longer & target throughput ok.... Yield/binning issues can be addressed.

Whilst there may be a per-wafer cost increase in SAQP over single-pass EUV*, it also means a lower upfront cost from not having to buy tens of EUV machines to fit out a line, in competition with many other fabs trying to buy them (driving prices and lead times up) and constraining production rates through lack of availability of first gen low-NA EUV machines.

Possible more interesting than China using DUV or EUV is how well they are doing on chiplet packaging: if they can sidestep the race for performance with reticle-busting leading-edge-process dies by skipping straight to disaggregated processors, that saves a lot of wasted R&D effort and time. That's the choice Intel has already made: eschewing reticle-limited low-NA EUV dies but instead going for smaller hign-NA EUV dies to combine with other dies and processes.

In the US, before the CHIPS act there was the DARPA CHIPS programme (Common Heterogeneous Integration and IP Reuse Strategies) for chiplet interoperability, followed by SHIP (which Intel took part in). Does China have a similar accelerated development programme?

* Note that current TSMC and Samsung EUV processes are using double-patterning low-NA EUV already anyway, so price/wafer is probably a wash.