Soft Machines Startup Promises 'Virtual Cores' Twice As Fast As Physical Cores

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This type of CPU is exactly what I've always thought of since I was a child. What I thought of is an octo core CPU that could virtually turn into one single core when necessary and separate into dual, triple, 5, hexa, 7 and octo core environments when needed.

Basically, their doing exactly what I thought of years ago. So cool that we can actually start making cpus that can do this!
 

qlum

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If this tech was used on amd it could seriously help them get back into business with their multicore cpu's being quite good at multithreaded performance but sucking at single threaded.
 

InvalidError

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With the extra complexity and latency of making out-of-order decisions in software, I would be skeptical about the conditions under which performance scaling can actually be achieved and how power-efficient the overall process would be. I find it ironic that putting OoE in the Atom is how Intel drastically improved Atom's performance per watt. Putting HT back in did not hurt either.

At least seeing the industry fork in three different paths should make things entertaining for a while.
 

yumri

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will it still be able to run windows 7, 8, 8.1, and 10? also will it be able to run all the programs made with the mind set of a x86 instruction set?
 


We won't know until soft machines makes a x86 version.
 

InvalidError

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Since Intel has not granted any other company a license for the x86 instruction set and AMD only has a non-transferable license, Soft Machine's CPU is almost certainly non-x86.

That thing probably runs the ARM instruction set on their proprietary non-ARM back-end, much like what Transmeta used to do with x86.
 

Mike Friesen

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Doesn't VIA still have an x86 licence? I doubt it's transferable, but I would't be too surprised for a band of chip veterans joining with VIA to make a new low-powered SoC. More likely though, it'll be very different from x86 or arm, because I think x86 is CISC and arm is RISC. Very different from VISC, I would assume, and if based on either, they would really just "become VISC" because if the thing that describes VISC is that it uses virtual cores.
 

Ori25

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ounds a little like backward progress. Software should use more cores not make one again. We will live and see how it goes...
 

InvalidError

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There used to be a handful of companies with x86 licenses but most of them have bailed out of the x86 business altogether.

Transmeta's chips were VLIW architecture - neither CISC nor RISC. They relied on a recompiler ("code morphing") firmware to take x86 code, translate it to VLIW, cache the output in reserved memory and execute from that. I'm guessing Soft Machines is going for something along those lines, albeit based on the ARMv7/8 instruction set.
 

kenjitamura

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Can't imagine this ever becoming a commercial competitor but maybe they can sell their patents to other chip makers and make a buck on the way out while improving existing technology.
 
Ummm...

A bit of a PROBLEM with this. Most software that is single-threaded will still NOT magically split the code in parallel just because you have virtually created a single core out of multiple cores.

Obviously you need the code to be capable of out-of-order coding.

The transition we need is mainly getting our SOFTWARE to be multi-threaded, not something like this with questionable real-world benefits.
 

d_kuhn

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Intersting idea and may be useful for some applications... but performance will be dependent on the code being accelerated (you won't see a uniform performance improvement). I definitely think it's an idea worth exploring though.
 

the_brute

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would love to see this coming to x86. the out of order issue wont be that big of a deal because the entire processer will be built for it, instead of running it right on a current processer.
Anyone want to lend AMD a few hundred million to buy this company?
 

theLiminator

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I could see this working for code programmed in a functional manner, however, imagine code written to be executed serially:

x = 0

for y in range(0, 10000):
x += y

print x

I am pretty sure it is impossible to parallelize this operation.

Overall, I am highly skeptical of their claims, and highly doubt that what they're doing is applies generally. They probably have UP to 2.1x execution speed.

I am sure there are many programs which will gain zero benefit from their technology.
 

zp3

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It would be much more sensible to bring finally FPGA structured processors to consumer market, but that would need a lot of reprogramming and standardisation for modern software products. But I'm sure somewhen mankind will see the need for it...
 

Jaroslav Jandek

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Issuing multiple instructions introduces overhead that does not scale well with performance => energy efficiency suffers. The latest Itanium is a good example: 12 instructions per cycle per core, slowest clock and the highest power consumption.

And this is done in HW! I am pretty sure practically simulating this functionality at a higher level of abstraction will introduce even more overhead. So while those CPUs would undeniably have higher single-thread performance, the energy efficiency would suffer greatly!
On the other hand, thread management and synchronization purely in SW introduces overhead as well... So this may be very interesting if done well.
 

Jaroslav Jandek

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Does not make much sense for cores with a low number of instructions per cycle... If you have a core with 2 IPC and split it to 4 HW threads, 2 virtual cores will be waiting every cycle...
Although it would be faster than context switching at the OS level (in the scheduler). But the complexity associated with that in the HW is not worth it, IMO.
 
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