News Solidigm's New Synergy 2.0 SSD Driver Claims up to 170% Speed Up

[Admin]

Solidigm has released the 2.0 version of its Synergy software solution, which includes a robust SSD toolkit and a drive-optimized driver. This means more features and better real-world performance for Solidigm SSDs.

Solidigm's New Synergy 2.0 SSD Driver Claims up to 170% Speed Up : Read more

 

[DMW888]

I just installed a fresh win 11 on my new P44 Pro 1tb then had a look at their software.

Synergy seemed rather useless considering their Storage tool app has nearly the same functionality, albeit without the fancy UI and 'Fast Lane', 'Clear Write Cache' setting options.

Both these options were unavailable to me however for whatever reason so I just kept Storage tool.

Message was "This operation can't be performed on this drive"

 

[bit_user]

Hmm, I like the host-managed caching. It would be nice if it let you "pin" certain files and directories to the cache, which would essentially prioritize them (but, they'd still have to get demoted to slower storage, as the drive's capacity nears full).

As for other stuff like smart-prefetch and posting writes from less-utilized CPU cores, those are optimizations I'd rather see the OS do. That's easier for the latter, but smart-prefetch fits in with host-managed caching because you need to store additional usage data to support it, which could be tricky if it's not built right into the filesystem.

Thinking about it some more, it seems like host-managed caching could be a standard NVMe thing. It wouldn't be supported across all drives, but it seems like you could add some advisory bits in the NVMe protocol that would enable cross-vendor implementations. That would enable the host management part to be handled by the OS, as well.

 

[thestryker]

A lot of what they're doing, and trying to do (gleaned from the L1T interview) is stuff that could be baked into the OS and/or be part of NVMe standards. It seemed like when the team worked at Intel there wasn't any interest from management to take any swings at improving things from the software side (if anyone isn't aware this team is the Intel NAND/storage team). I think a lot of optimizations will be very important as the industry tries to move beyond QLC to drive their costs down further.

Here's the L1T interview for anyone who didn't come from the other storage thread:

View: https://www.youtube.com/watch?v=8YBeriMsDS0

 

[bit_user]

I think a lot of optimizations will be very important as the industry tries to move beyond QLC to drive their costs down further.

As you're probably aware, the capacity yielded by packing more bits/cell increases 1/x. So, you only get 25% more capacity by going to 5 bits per cell, yet you're cutting in half the voltage difference between two states, making it much more prone to noise and dramatically reducing power-off data retention time. Plus, you need more error-correction overhead, which should even cut down that 25% figure by a little bit.

In other words, I sure hope the industry doesn't go to 5 bits, but that will probably happen for at least bottom-tier consumer flash. The only good thing about it is the improvements in cell design that enable PLC should also benefit lower-density NAND.