So apparently a Ryzen 3900X is basically just two 3600X's put together. There's like 2 die sets called chiplets or something.... How is this different then the "modules" amd was using 4 or 5 years back? They had chips that were like 4 modules 8 cores and only 1 instruction could be in the modules pipeline at a time meaning 4 of the cores were useless..... Can anyone explain this? Maybe this was all wrong but I can't find anything that clearly explains how this works and.... And also what's the difference between dual-6-core chiplets and 1 12 core Chiplet? Anyone????
Question Someone want to explain this whole Chiplet thing?
- Thread starter ch33r
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- Mar 16, 2013
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Those are some of the ones I was reading. They explain the benefits of chiplets pretty good. What I don't understand is why chiplets are being used instead of 12 straight cores, and how this is different then the modules they were using a few years back. Also, what are the drawbacks and why are they doing this? It makes no sense
- Mar 16, 2013
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"With its third-generation Ryzen CPUs, AMD has chosen to split its I/O and DRAM controllers into a single functional block, while its CPU cores and L3 cache are contained within each individual chiplet. "
It's simply a new word for how they built the thing. It doesn't really mean anything.
Different parts and functions in different sections of the die.
It's not any better or worse than any other architecture.
It's simply a new word for how they built the thing. It doesn't really mean anything.
Different parts and functions in different sections of the die.
It's not any better or worse than any other architecture.
Ok.... The reason I'm asking is because I remember the old module concept came out apparently only 1 instruction could be in a modules pipeline at a time making half the cores useless. I don't know if this is true or not but how is this different then what we're doing now? I don't understand how this all works, especially why were doing 2 chiplets with 6 cores instead of just 12 cores
- Mar 16, 2013
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There is not a performance hit either way, because the term "chiplet" is a made up marketing/engineering word for how they constructed this line of CPUs.
If they had used the word 'section', or 'quadrant', or 'sectlet', or 'Patio1/2/3/4'....would that make a difference?
- Mar 16, 2013
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One would assume that this is the way it works best, given the constraints of physics, current manufacturing tolerances, and cost to manufacture.
Your main question doesn't really make sense.
A "chiplet" is not a thing. It conveys no performance increase or decrease.
It is merely what they call different sections of the CPU die.
- Jun 19, 2011
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Likely better yields. The more you cram on a single piece of silicon the higher the chance of failure.
- Mar 16, 2013
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It's not different, actually. Lose the word 'chiplet', and just think of it as 'module'.
Time marches on.
Capabilities increase.
Die traces shrink, leading to more "components" in a single CPU, leading to more work being done for a single CPU clock cycle.
Leading to more game FPS, or faster database responses, or less power consumption for the same amount of data.
The two main reasons to go with a chiplet design are much higher yields and ease of scaleability. A large die, high core count, monolithic chip is going to have a high percentage of chips that fail due to manufacturing imperfections. It only takes 1 flaw to ruin an expensive piece of silicone.
Say on average you have a flaw every 200 sq mm and you are building a large 300 sq mm single monolithic chip. Odds are you are going to have a lot of failed chips. However if you have 100 sq mm chiplets your yields drastically increase.
Scalibility is also much simpler. Instead of having to design and tool for each individual CPU and their varying core counts you can simply add or subtract a "core" complex to a standard IO controller to full a product sku.
How are they different?, that is a complex question but in the simplest terms I would say AMD's new chiplet design is more similar to older "standard" monolithic designs they are just made of smaller pieces where as the FX lineup were something very different from a design standpoint.
What are some disadvantages? I think the largest may be latency. Since chiplets are separate silicone complexes there is a void between different aspects that then need to be connected. This space adds a little latency but AMD have done a very good job of minimizing this.
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the connection between the different parts of the die is a lot better/faster than it was before. they also learned other lessons and changed how the data flowed between the modules.
the difference between what they chose to do vs other architecture is a different way to communicate between and route data between the various parts. how you arrange the parts and how you connect them relates to overall speed and efficiency of the design.
12 "cores" in a line means certain cores are near the end of the data stream, creating latency and other things that slow down the data flow. bunching 6 of them together on one side and 6 on the other with traffic control in the middle shortens the route and so on. there are other ways to do it but this is how AMD has chosen to do it. its complicated but this is one way to think of the layout they use.
scaling is important as well. if you can simply connect multiple groups of cores together. it's rather easy to create chips with more cores as needed. so rather than having to redesign it for 12 cores vs 6. you simply connect another 6 core "chiplet" and then you have a 12 core. connect another and 18 cores and so on. ease of scaling is part of the design and something focused on by everyone. stick one or 2 together for consumer grade, then another 4 and you got enterprise class product with little extra effort.
the difference between what they chose to do vs other architecture is a different way to communicate between and route data between the various parts. how you arrange the parts and how you connect them relates to overall speed and efficiency of the design.
12 "cores" in a line means certain cores are near the end of the data stream, creating latency and other things that slow down the data flow. bunching 6 of them together on one side and 6 on the other with traffic control in the middle shortens the route and so on. there are other ways to do it but this is how AMD has chosen to do it. its complicated but this is one way to think of the layout they use.
scaling is important as well. if you can simply connect multiple groups of cores together. it's rather easy to create chips with more cores as needed. so rather than having to redesign it for 12 cores vs 6. you simply connect another 6 core "chiplet" and then you have a 12 core. connect another and 18 cores and so on. ease of scaling is part of the design and something focused on by everyone. stick one or 2 together for consumer grade, then another 4 and you got enterprise class product with little extra effort.
- Mar 16, 2013
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- Mar 16, 2013
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Exactly.
Just as you cannot directly compare "2 chiplets with 6 cores" with "12 cores".
Architecture, and how it was designed and coded.
- Mar 16, 2013
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As mentioned above, manufacturing yield might be one consideration.
The actual issue would probably only be gained by interviewing AMD engineers, and signing a strict NDA.
- Mar 16, 2013
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It's not consumers.
It is Intel/Samsung/Micron that they don't want to know their internal secrets.
And 99.999% of 'consumers' don't care about the marketing semantics between core and module and chiplet.
Ok, so question. If I disabled 2 of the cores in each of those chiplets, so it was 2 chiplets with 4 cores each, and benched it against a 3800X, which has one chiplet and 8 cores, which one would win the benchmarks, assuming all the other components in the case are exactly the same
- Mar 16, 2013
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That is absolutely impossible to predict, without either serious in depth knowledge of how this was built, or direct clean room testing.
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