News Sony PlayStation 3 emulator RPCS3 now natively supports Arm64 architecture — including Raspberry Pi 5

ezst036

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This is quite interesting. Wasn't PS3 the last to use Cell? And if so, isn't that somewhat structured around IBM's PowerPC ISA? Its rather interesting if that is the case that there is a potentially lowered emulation hit going from one type of RISC to another type of RISC.(or if its just that ARM and PPC have a lot of similarities)

In any case, I think PS4 moved to AMD's jaguar chips. That bodes well for the next generation PS emulation taking performance really well the other way. Technically, it shouldn't have to be emulated at all in the traditional sense since its already running x86.
 

bit_user

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Wasn't PS3 the last to use Cell? And if so, isn't that somewhat structured around IBM's PowerPC ISA?
I think it was the only really successful use of the Cell. I know the Cell got limited use in some HPC contexts, but I'd be surprised if the revenue from those efforts ever amounted to much.

Its rather interesting if that is the case that there is a potentially lowered emulation hit going from one type of RISC to another type of RISC.(or if its just that ARM and PPC have a lot of similarities)
Yeah, I had similar thoughts. Maybe there's less impedance mismatch, between those ISAs. Perhaps a lot depends on how well ARM Neon matches the Cell's vector extensions. The main horsepower of the Cell really lies in the SPEs and their vector pipelines, so how well you can emulate those seems key.

Since the SPEs each have 256 kB of SRAM, another big factor is probably having plenty of fast L2 cache, so the SPE data stays "hot". According to what I can find, the Pi 5 has:
  • 64KByte I and D caches
  • 512KB L2 per core
  • 2MB shared L3

So, perhaps its cache configuration meets the bare minimum? Depends somewhat on whether the GPU also shares the L3, I think.

Also, sticking with the theme of SPEs, because the PS3 had 6 of them (enabled and available to games, at least), it is a little surprising a mere 4-core Pi 5 would be competent at emulation. I'd expect RPCS3 to strongly favor 8-core CPUs, since that gives you full concurrency of the 6 SPEs + PPE, with a core to spare for OS stuff.

SPE_%28cell%29.png

Source: https://en.wikipedia.org/wiki/Cell_(processor)
 
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bit_user

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Now that I think about it, I'm really wondering whether RPCS3 uses SMT/hyperthreading to emulate the async DMA functionality of the SPEs. If you had an 8-core CPU with HT/SMT, you could try to use affinity masks to pair one thread running the compute workload of each SPE with another thread devoted to doing its DMA transfers. The advantage would be most apparent if some games or rendering/physics engines use the SPEs in a tightly-synchronized way.

IMO, the fact that it took so long to achieve competent emulation of a PS3 is a further testament to the power of The Cell. I think of it a little like an adaptation of a CPU-like architecture to do GPU-like compute.
 
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P.Amini

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Now that I think about it, I'm really wondering whether RPCS3 uses SMT/hyperthreading to emulate the async DMA functionality of the SPEs. If you had an 8-core CPU with HT/SMT, you could try to use affinity masks to pair one thread running the compute workload of each SPE with another thread devoted to doing its DMA transfers. The advantage would be most apparent if some games or rendering/physics engines use the SPEs in a tightly-synchronized way.

IMO, the fact that it took so long to achieve competent emulation of a PS3 is a further testament to the power of The Cell. I think of it a little like an adaptation of a CPU-like architecture to do GPU-like compute.
Or maybe because Cell is harder to program?