An addressing mode with regards to computer instruction sets is basically a way to get the data you want. For example if you want store data somewhere, you can:
- Give it an immediate value (store the value 2000 in memory location 1000)
- The value in a memory address (copy the value in address 2000 in memory location 1000)
Now these are straight forward and relatively easy to understand. However, there were also:
- Look at the value in a memory address, then use that value as the memory address on where to store data to (copy the value in the address pointed to by the value in address 2000 in memory location 1000)
- Calculate the address by using the values in two memory locations, the first address containing a start point, the second address containing how far from the that start point (copy the value by adding the values in memory addresses 2000 and 2001, use the result as the address location to look into, then store that in memory location 1000)
- Calculate the address by using the values in three memory locations, the first containing a start point, the second containing a scale factor (so start * scale), the third containing how far from that to look into.
There are plenty of variations between the last two points. What a lot of RISC ISAs did was remove the last two ways to address memory. The reason is because of the amount of extra overhead it costs to calculate the actual address. The main point of RISC was to reduce the amount of overhead it takes to execute each instruction.
So why even have these addressing modes in the first place? The primary reason was to make the code denser. You can do all of these addressing modes with simpler commands instead, but that also means your program is bigger because there's more instructions to run. For example, you could break down the process of how to open a door with a knob (put hand on the door knob, turn the knob, push the door) or you could just say "open the door."
The second reason, I think, was technical. Home computer CPUs way back when RISC was first developed (in the late 70s through the 80s) could only process 8 or 16 bits at once, but how many memory locations the CPU could address or needed to address often exceeded how many you could have in either an 8-bit value (256 locations) or 16-bit value (65536 locations).
Here's a famous example, the segmented memory system used by Intel's 8086. The 8086 was a 16-bit CPU with a 20-bit memory address. If it can only process 16-bits at once, how can it calculate a 20-bit address? By using two different registers called the segment and offset. The CPU would automatically calculate the address by taking the segment register, padding it with 4 more bits (so a value of 0x1234 5678 in the segment register would be padded to 0x1234 5678 00), then adding the offset register to that value. This had a quirk that you could address the same memory location in multiple ways. Say you wanted to access memory location 0x1234 5678 11. You could do this by using the value 0x1234 5678 in the segment register and 0x0000 0011 in the offset register. Or you could use the value 0x1234 5677 in the segment register and 0x0000 0111 in the offset register. Thanks to this quirk, this led to an infamous issue know simply as
A20 Line. The short of it is, because lots of programmers abused this quirk, it led to huge compatibility issues when Intel made the 80286 with its 24-bit memory address space.
By the time RISC processors became commercially viable, they were 32-bit CPUs with 32-bits of memory address space, so there wasn't really a need to do something like what the 8086 did.
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