tccdl and tccd

[Amir_yazd]

Hi,

I am trying to get a better understanding about memory timing. There is a timing constraint in GDDR5 called tccdl. It defines the number of clock cycles between read/write from bank A to read/write from bank B in the same bankgroup.

(1) Does this timing means that after tccdl all the data from bank A is sent to memory controller?
(2) How come tccdl is more than tccd?
(3) If I add a special buffer (size of global IOs) to the global IO which read the whole data every cycle, can I reduce the tccdl to one cycle? Can I issue one read request to a bank every cycle?

I appreciate any help.

Thanks
- Amir

 

[Pinhedd]

Hi,

I am trying to get a better understanding about memory timing. There is a timing constraint in GDDR5 called tccdl. It defines the number of clock cycles between read/write from bank A to read/write from bank B in the same bankgroup.

(1) Does this timing means that after tccdl all the data from bank A is sent to memory controller?
(2) How come tccdl is more than tccd?
(3) If I add a special buffer (size of global IOs) to the global IO which read the whole data every cycle, can I reduce the tccdl to one cycle? Can I issue one read request to a bank every cycle?

I appreciate any help.

Thanks
- Amir

Hi Amir,

Tccd is the number of cycles that must be allowed to elapse between successive column commands, specifically from one read command to another read command or from one write command to another write command. On DDR, DDR2, and DDR3 Tccd is a function of the prefetch depth. Since DDR3 has aprefetch depth of 8 words, and 2 words are transferred per cycle, no less than 4 cycles must elapse between successive column commands made to any bank to prevent data from getting clobbered.

On SDR, DDR, DDR2, and DDR3 each memory bank is fully independent. As long as Tccd is respected, no issues will occur regardless of which bank a command is sent to. GDDR5 introduces a concept called "bank groups", this same concept was adopted by DDR4 so my explanation applies equally to that architecture as well.

In GDDR5, each bank group is independent of all other bank groups but banks within each bank group are not independent from eachother. There are four bank groups with each bank group containing four banks for a total of sixteen banks.

Tccd_short is the number of cycles that must elapse between column commands between banks in different bank groups

Tccd_long is the number of cycles that must elapse between column commands between banks in the same bank group.

The impact of this arrangement is that it is no longer possible to tightly pipeline column commands between any two arbitrary banks, only between arbitrary bank groups.

To answer your specific questions:

1. No. The memory controller will have all of the data from the read request after Tcl + Tburst cycles. A write will be complete after Tburst + Tcwl cycles.

2. Explained above, it's due to an architectural change. It's too difficult to have 16 independent banks; bank grouping is necessary to keep power consumption down, conserve on-chip realestate, and keep the IO interface fast.

3. No. At most, one column command can be issued every Tccd_short cycles. They need not be aligned, commands simply cannot overlap without causing data corruption. Other commands such as Row Active and Precharge can be issued whenever as long as their respective timings are met.

 

[Amir_yazd]

Based on your answer, if I add a buffer with the size of internal buswidth of DDR3 to the GIO, then I can issue a column command every cycle. Suppose I want to use the data internally in the DRAM and I WON't send it outside the DRAM chip at all. It works like this:

clock cycle 0: issue the column command, the data will be on the GIOs and my special buffer capture the data
clock cycle 1: issue another column command, the data will be on the GIOs and my special buffer capture it
and so on

What is the nature of tCCDL/tCCDS? Do you have any reference?
tCCDL = the amount of cycles that is needed for sending the data out of DRAM chip?

Hi,

I am trying to get a better understanding about memory timing. There is a timing constraint in GDDR5 called tccdl. It defines the number of clock cycles between read/write from bank A to read/write from bank B in the same bankgroup.

(1) Does this timing means that after tccdl all the data from bank A is sent to memory controller?
(2) How come tccdl is more than tccd?
(3) If I add a special buffer (size of global IOs) to the global IO which read the whole data every cycle, can I reduce the tccdl to one cycle? Can I issue one read request to a bank every cycle?

I appreciate any help.

Thanks
- Amir

Hi Amir,

Tccd is the number of cycles that must be allowed to elapse between successive column commands, specifically from one read command to another read command or from one write command to another write command. On DDR, DDR2, and DDR3 Tccd is a function of the prefetch depth. Since DDR3 has aprefetch depth of 8 words, and 2 words are transferred per cycle, no less than 4 cycles must elapse between successive column commands made to any bank to prevent data from getting clobbered.

On SDR, DDR, DDR2, and DDR3 each memory bank is fully independent. As long as Tccd is respected, no issues will occur regardless of which bank a command is sent to. GDDR5 introduces a concept called "bank groups", this same concept was adopted by DDR4 so my explanation applies equally to that architecture as well.

In GDDR5, each bank group is independent of all other bank groups but banks within each bank group are not independent from eachother. There are four bank groups with each bank group containing four banks for a total of sixteen banks.

Tccd_short is the number of cycles that must elapse between column commands between banks in different bank groups

Tccd_long is the number of cycles that must elapse between column commands between banks in the same bank group.

The impact of this arrangement is that it is no longer possible to tightly pipeline column commands between any two arbitrary banks, only between arbitrary bank groups.

To answer your specific questions:

1. No. The memory controller will have all of the data from the read request after Tcl + Tburst cycles. A write will be complete after Tburst + Tcwl cycles.

2. Explained above, it's due to an architectural change. It's too difficult to have 16 independent banks; bank grouping is necessary to keep power consumption down, conserve on-chip realestate, and keep the IO interface fast.

3. No. At most, one column command can be issued every Tccd_short cycles. They need not be aligned, commands simply cannot overlap without causing data corruption. Other commands such as Row Active and Precharge can be issued whenever as long as their respective timings are met.

 

[Pinhedd]

Based on your answer, if I add a buffer with the size of internal buswidth of DDR3 to the GIO, then I can issue a column command every cycle. Suppose I want to use the data internally in the DRAM and I WON't send it outside the DRAM chip at all. It works like this:

clock cycle 0: issue the column command, the data will be on the GIOs and my special buffer capture the data
clock cycle 1: issue another column command, the data will be on the GIOs and my special buffer capture it
and so on

What is the nature of tCCDL/tCCDS? Do you have any reference?
tCCDL = the amount of cycles that is needed for sending the data out of DRAM chip?

Hi,

I am trying to get a better understanding about memory timing. There is a timing constraint in GDDR5 called tccdl. It defines the number of clock cycles between read/write from bank A to read/write from bank B in the same bankgroup.

(1) Does this timing means that after tccdl all the data from bank A is sent to memory controller?
(2) How come tccdl is more than tccd?
(3) If I add a special buffer (size of global IOs) to the global IO which read the whole data every cycle, can I reduce the tccdl to one cycle? Can I issue one read request to a bank every cycle?

I appreciate any help.

Thanks
- Amir

Hi Amir,

Tccd is the number of cycles that must be allowed to elapse between successive column commands, specifically from one read command to another read command or from one write command to another write command. On DDR, DDR2, and DDR3 Tccd is a function of the prefetch depth. Since DDR3 has aprefetch depth of 8 words, and 2 words are transferred per cycle, no less than 4 cycles must elapse between successive column commands made to any bank to prevent data from getting clobbered.

On SDR, DDR, DDR2, and DDR3 each memory bank is fully independent. As long as Tccd is respected, no issues will occur regardless of which bank a command is sent to. GDDR5 introduces a concept called "bank groups", this same concept was adopted by DDR4 so my explanation applies equally to that architecture as well.

In GDDR5, each bank group is independent of all other bank groups but banks within each bank group are not independent from eachother. There are four bank groups with each bank group containing four banks for a total of sixteen banks.

Tccd_short is the number of cycles that must elapse between column commands between banks in different bank groups

Tccd_long is the number of cycles that must elapse between column commands between banks in the same bank group.

The impact of this arrangement is that it is no longer possible to tightly pipeline column commands between any two arbitrary banks, only between arbitrary bank groups.

To answer your specific questions:

1. No. The memory controller will have all of the data from the read request after Tcl + Tburst cycles. A write will be complete after Tburst + Tcwl cycles.

2. Explained above, it's due to an architectural change. It's too difficult to have 16 independent banks; bank grouping is necessary to keep power consumption down, conserve on-chip realestate, and keep the IO interface fast.

3. No. At most, one column command can be issued every Tccd_short cycles. They need not be aligned, commands simply cannot overlap without causing data corruption. Other commands such as Row Active and Precharge can be issued whenever as long as their respective timings are met.

Hi,

Tccds = Tccd_Short
Tccdl = Tccd_Long

Both are explained above

On DDR4 and GDDR5 Tccd_Short should always be 4 command cycles regardless of the command clock frequency
Tccd_Long may be as low as 4 command cycles at low data rates (effectively eliminating the issue described previously) but will increase as data rate increases.

I'm not quite sure what you mean by "adding a buffer". Each DRAM bank is fronted by a row buffer which the active row is latched into. For DDR3 the row is 8192 bits wide for 4-bit word and 8-bit word chips, and 16384 bits wide for 16-bit word chips. During a read operation, 8 words from the row buffer are selected and serialized into the IO logic which eventually makes its way to the GIO. The opposite occurs during a write operation, 8 words from the GIO are deserialized and latched into the selected bank.

Tccd is necessary to prevent these operations from colliding. Issuing a read command to bank 0 will result in a burst of 8 words on the IO pins over 4 cycles starting Tcl cycles later. Issuing a read command to bank 1 will result in a burst of 8 words on the IO pins over 4 cycles starting Tcl cycles later. If the read command to bank 1 is issued less than 4 cycles after tha read command to bank 0 then the operations will collide and is thus subject to the specified collision behaviour.

Whereas Tcas may be 9 cycles, and the DRAM chip thus takes 9 cycles to begin producing data from a read command, Tccd may be only 4 cycles. This allows read and write commands to be interleaved to multiple banks at once. That is, a subsequent read command can be issued before a previous read command has completed. The same is true for write commands.

 

[Amir_yazd]

Thanks a lot for your help.

I am doing research in computer architecture and I am trying to propose new microarchitecture for DRAM
This is why I asked supposedly if I add another big buffer (it is not row buffer) attached to GIOs inside a DRAM chip, I should be able to issue a read command every cycle without contaminating the data.

I apologize if I can not explain it well.

Based on your answer, if I add a buffer with the size of internal buswidth of DDR3 to the GIO, then I can issue a column command every cycle. Suppose I want to use the data internally in the DRAM and I WON't send it outside the DRAM chip at all. It works like this:

clock cycle 0: issue the column command, the data will be on the GIOs and my special buffer capture the data
clock cycle 1: issue another column command, the data will be on the GIOs and my special buffer capture it
and so on

What is the nature of tCCDL/tCCDS? Do you have any reference?
tCCDL = the amount of cycles that is needed for sending the data out of DRAM chip?

Hi,

I am trying to get a better understanding about memory timing. There is a timing constraint in GDDR5 called tccdl. It defines the number of clock cycles between read/write from bank A to read/write from bank B in the same bankgroup.

(1) Does this timing means that after tccdl all the data from bank A is sent to memory controller?
(2) How come tccdl is more than tccd?
(3) If I add a special buffer (size of global IOs) to the global IO which read the whole data every cycle, can I reduce the tccdl to one cycle? Can I issue one read request to a bank every cycle?

I appreciate any help.

Thanks
- Amir

Hi Amir,

Tccd is the number of cycles that must be allowed to elapse between successive column commands, specifically from one read command to another read command or from one write command to another write command. On DDR, DDR2, and DDR3 Tccd is a function of the prefetch depth. Since DDR3 has aprefetch depth of 8 words, and 2 words are transferred per cycle, no less than 4 cycles must elapse between successive column commands made to any bank to prevent data from getting clobbered.

On SDR, DDR, DDR2, and DDR3 each memory bank is fully independent. As long as Tccd is respected, no issues will occur regardless of which bank a command is sent to. GDDR5 introduces a concept called "bank groups", this same concept was adopted by DDR4 so my explanation applies equally to that architecture as well.

In GDDR5, each bank group is independent of all other bank groups but banks within each bank group are not independent from eachother. There are four bank groups with each bank group containing four banks for a total of sixteen banks.

Tccd_short is the number of cycles that must elapse between column commands between banks in different bank groups

Tccd_long is the number of cycles that must elapse between column commands between banks in the same bank group.

The impact of this arrangement is that it is no longer possible to tightly pipeline column commands between any two arbitrary banks, only between arbitrary bank groups.

To answer your specific questions:

1. No. The memory controller will have all of the data from the read request after Tcl + Tburst cycles. A write will be complete after Tburst + Tcwl cycles.

2. Explained above, it's due to an architectural change. It's too difficult to have 16 independent banks; bank grouping is necessary to keep power consumption down, conserve on-chip realestate, and keep the IO interface fast.

3. No. At most, one column command can be issued every Tccd_short cycles. They need not be aligned, commands simply cannot overlap without causing data corruption. Other commands such as Row Active and Precharge can be issued whenever as long as their respective timings are met.

Hi,

Tccds = Tccd_Short
Tccdl = Tccd_Long

Both are explained above

On DDR4 and GDDR5 Tccd_Short should always be 4 command cycles regardless of the command clock frequency
Tccd_Long may be as low as 4 command cycles at low data rates (effectively eliminating the issue described previously) but will increase as data rate increases.

I'm not quite sure what you mean by "adding a buffer". Each DRAM bank is fronted by a row buffer which the active row is latched into. For DDR3 the row is 8192 bits wide for 4-bit word and 8-bit word chips, and 16384 bits wide for 16-bit word chips. During a read operation, 8 words from the row buffer are selected and serialized into the IO logic which eventually makes its way to the GIO. The opposite occurs during a write operation, 8 words from the GIO are deserialized and latched into the selected bank.

Tccd is necessary to prevent these operations from colliding. Issuing a read command to bank 0 will result in a burst of 8 words on the IO pins over 4 cycles starting Tcl cycles later. Issuing a read command to bank 1 will result in a burst of 8 words on the IO pins over 4 cycles starting Tcl cycles later. If the read command to bank 1 is issued less than 4 cycles after tha read command to bank 0 then the operations will collide and is thus subject to the specified collision behaviour.

Whereas Tcas may be 9 cycles, and the DRAM chip thus takes 9 cycles to begin producing data from a read command, Tccd may be only 4 cycles. This allows read and write commands to be interleaved to multiple banks at once. That is, a subsequent read command can be issued before a previous read command has completed. The same is true for write commands.