News Tests indicate Intel's '200S Boost' feature provides no real gain for Arrow Lake CPUs on Linux

[Admin]

Phoronix's testing shows that Intel's 200S Boost feature yields little to no performance improvements with the same RAM kit.

Tests indicate Intel's '200S Boost' feature provides no real gain for Arrow Lake CPUs on Linux : Read more

 

[Stomx]

This year both Intel and AMD will deliver their new chips made by their Oregon and Arizona latest fab 0.019874 nm technology. Versus previous year 0.02 nm technology chips this will bring 0.044% improvement in fps, TOPS, FP2 and FP4. Major BIOSes already made them compatible with all existing motherboards made after 2035 with additional improvements in speed by up to whopping 0.0005353%

 

[thestryker]

None of the links in the article appear to have a link to the Phoronix article (I may have just missed it) so just in case: https://www.phoronix.com/review/intel-200s-boost-linux

While modifying NGU clocks don't do much increasing D2D clocks lowers memory latency. So while it will make a noticeable difference for particularly sensitive workloads it doesn't do much outside of that. I believe Hitman 3 is one of the more memory sensitive games and I think one of the Ubisoft engines is as well, but I don't recall which one.

 

[TerryLaze]

News - Intel Core Ultra 9 285K performance sees 6% improvement on Linux — Arrow Lake boosts even without new '200S Boost' BIOS

Six months after its commercial release, a recently re-tested Intel Core Ultra 9 285K shows a 6% performance boost, thanks to BIOS revisions and better P/E core scheduling. Intel Core Ultra 9 285K performance sees 6% improvement on Linux — Arrow Lake boosts even without new '200S Boost' BIOS ...

forums.tomshardware.com

Well, linux already had the same amount of improvement that the boost provides without the boost so it makes sense that the boost doesn't boost the boost even boostier.

 

[TerryLaze]

This year both Intel and AMD will deliver their new chips made by their Oregon and Arizona latest fab 0.019874 nm technology. Versus previous year 0.02 nm technology chips this will bring 0.044% improvement in fps, TOPS, FP2 and FP4. Major BIOSes already made them compatible with all existing motherboards made after 2035 with additional improvements in speed by up to whopping 0.0005353%

Well unless you come up with a way to make individual atoms behave like they are completely isolated from physics then that's where technology is at the moment, we can only make baby steps because physics is a cruel mistress and doesn't allow us to do what we want.

 

[Pierce2623]

Well unless you come up with a way to make individual atoms behave like they are completely isolated from physics then that's where technology is at the moment, we can only make baby steps because physics is a cruel mistress and doesn't allow us to do what we want.

Just because node gains tapered off doesn’t mean IPC has to as well. If they’d get the creative juices flowing I’m sure we could get more IPC increases. As long as the big boys continue to only make core pipelines wider with larger out of order engines, sure node gains are need to even realize those IPC gains but some out of the box thinking could shake things up.

 

[JRStern]

Not a big surprise, takes a lot of balancing to make all the parts play together now, can't just drop a faster crystal on the motherboard and get speed, like I did with my IBM PC-AT circa 1986.
Besides, 99% of PC users don't care, an i5 running stock is plenty for them.

 

[Amdlova]

@JRStern I have here a 14700T Pl1 50w PL2 105w Fassssssssssssssssssssssst as hell 4.8ghz with 50w Intel make notebook cpus for desktops from 4.8ghz to 5.5ghz need to push more 200w! lol

 

[TerryLaze]

Just because node gains tapered off doesn’t mean IPC has to as well. If they’d get the creative juices flowing I’m sure we could get more IPC increases. As long as the big boys continue to only make core pipelines wider with larger out of order engines, sure node gains are need to even realize those IPC gains but some out of the box thinking could shake things up.

No, to get more IPC you have to literally find a way to make electrons "move faster" so you can switch transistors from on to off faster, one way of doing that is to just make the distance they have to travel shorter, hence smaller nodes.
The other way would be to change the laws of physics....

Or to go to different materials which would allow the electrons to move faster but humanity is trying that for decades now with very little progress.

Micromanaging the flow with wider pipelines and OoO (or huge caches like the x3d) and so on is the only thing they can do.

 

[Pierce2623]

No, to get more IPC you have to literally find a way to make electrons "move faster" so you can switch transistors from on to off faster, one way of doing that is to just make the distance they have to travel shorter, hence smaller nodes.
The other way would be to change the laws of physics....

Or to go to different materials which would allow the electrons to move faster but humanity is trying that for decades now with very little progress.

Micromanaging the flow with wider pipelines and OoO (or huge caches like the x3d) and so on is the only thing they can do.

Switching transistors on and off faster is the freaking opposite of IPC increases….. That’s literally a clock speed increase…because of that being so far off base, I’m not even bothering with the rest.

 

[TerryLaze]

Switching transistors on and off faster is the freaking opposite of IPC increases….. That’s literally a clock speed increase…because of that being so far off base, I’m not even bothering with the rest.

So you don't agree with them making the cores wider to actually get more instructions done per cycle and you are also against them increasing the amount of cycles to increase the performance in that way......
So you just want magic, "just do it" .

 

[NinoPino]

So you don't agree with them making the cores wider to actually get more instructions done per cycle and you are also against them increasing the amount of cycles to increase the performance in that way......
So you just want magic, "just do it" .

A lot of methods permit to increase performance without magics, clock or wider cores.
The sense of @Pierce2623 's post is, that it is easy to enlarge the design or makes it deeper, but the gains, are smaller and smaller, wider and deeper we go. A more organic design of the CPU, allow to obtain greater generational improvements.

 

[TerryLaze]

A lot of methods permit to increase performance without magics, clock or wider cores.

Yes and all of them are always being done, that's all the extensions the CPU has as well as the instruction set, these have been, and keep getting, refined and optimized for 50 years now.
These where huge during the beginning of the CPUs when they where just figuring out how do this stuff, now because of 50 years of refinement they are minimal improvements that won't be measurable even with benchmarks because it is a drop in an ocean compared to the rest of the CPU.

You can't make an instruction faster just by wanting it to be faster, you can make the data be copied faster (wider bus) or you can make the cpu be able to use more data in one go (wider cpu core) what you can not do is to tell the CPU "just be faster, dude" ,unless you increase the cycles per second.

A more organic design of the CPU, allow to obtain greater generational improvements.

How do you design a digital thing to be more organic?!?!?
They put new extension in the CPU whenever they think that the market can and will use them, like AES AVX and so on, or they even put new hardware in, like now NPU to do something new that the market expects.

 

[NinoPino]

Yes and all of them are always being done, that's all the extensions the CPU has as well as the instruction set, these have been, and keep getting, refined and optimized for 50 years now.

So, are you saying that there is no room for improvements ? I remember that, in the past, somebody said something similar about phisics.

These where huge during the beginning of the CPUs when they where just figuring out how do this stuff, now because of 50 years of refinement they are minimal improvements that won't be measurable even with benchmarks because it is a drop in an ocean compared to the rest of the CPU.

The Core architecture was a minimal improvement ?
The Apple ARM architecture was a minimal improvement ?
The Zen architecture was a minimal improvement ?

You can't make an instruction faster just by wanting it to be faster,

you can make the data be copied faster (wider bus) or you can make the cpu be able to use more data in one go (wider cpu core) what you can not do is to tell the CPU "just be faster, dude" ,unless you increase the cycles per second.

But if you change the logic, you can achieve big improvements. Examples can be found in the past for countless types of instructions.

How do you design a digital thing to be more organic?!?!?

Redesign a big portion of the CPU for example.

They put new extension in the CPU whenever they think that the market can and will use them, like AES AVX and so on, or they even put new hardware in, like now NPU to do something new that the market expects.

And this is exactly the example of big performance improvement made without clock, wider design or deeper pipeline. As @Pierce2623 initially suggested but you do not agreed.

 

[TerryLaze]

The Core architecture was a minimal improvement ?
The Apple ARM architecture was a minimal improvement ?
The Zen architecture was a minimal improvement ?

Apple changed from cisc to risc ,from a general purpose cpu to a specialist cpu, what you say is like doing raytracing on the cpu and on the gpu and then saying that the gpu has higher IPC... they are different things.

AMD fixed the issues of faildozer that had very narrow cores and shared resources between multiple cores, zen made the cores wider and didn't share resources.

But if you change the logic, you can achieve big improvements. Examples can be found in the past for countless types of instructions.


Redesign a big portion of the CPU for example.

But they already did that.

And this is exactly the example of big performance improvement made without clock, wider design or deeper pipeline. As @Pierce2623 initially suggested but you do not agreed.

I was the one that said that they are doing this already as much as they can.

 

[Pierce2623]

So you don't agree with them making the cores wider to actually get more instructions done per cycle and you are also against them increasing the amount of cycles to increase the performance in that way......
So you just want magic, "just do it" .

Where did I say making the cores wider is bad? I said if that approach is slowing down then maybe some out of the box thinking could help. Funnily enough, over the last 4-5 years, AMD has been the slowest in adopting the wider wider wider approach. That’s served them quite well. Zen5 was the first major increase in pipeline width on Zen and the smallest performance gain. No im not saying wider cores are bad. I’m saying adopting that as the only major lever for increasing IPC is bad. I’m not even saying anyone has done that though. Well maybe Intel has. Their damn e cores are literally wider than Zen5.

 

[NinoPino]

Apple changed from cisc to risc ,from a general purpose cpu to a specialist cpu, what you say is like doing raytracing on the cpu and on the gpu and then saying that the gpu has higher IPC... they are different things.

I was talking of Apple ARM design vs standard ARM Ltd design.

 

[Eximo]

RISC is not a specialist CPU, it is reduced instruction set by definition and ends up relying more on software than hardware to produce results. If anything, CISC based x86 is the specialist architecture with its many instruction sets for specific tasks which requires less software.

Though I would argue that the concept has become more muddied since, Apple in particular, many ARM/RISC chips have large sections of the CPU dedicated to specific tasks anyway.

 

[Pierce2623]

Apple changed from cisc to risc ,from a general purpose cpu to a specialist cpu, what you say is like doing raytracing on the cpu and on the gpu and then saying that the gpu has higher IPC... they are different things.

AMD fixed the issues of faildozer that had very narrow cores and shared resources between multiple cores, zen made the cores wider and didn't share resources.

But they already did that.

I was the one that said that they are doing this already as much as they can.

The fact that you think there’s something “specialist” about RISC means this conversation is over. I’m not doing the RISC vs CISC thing. NEITHER is inherently more performant or more efficient. Yes risc has shorter instructions but it generally takes more instructions to do the same amount of work.

 

[TerryLaze]

Yes risc has shorter instructions but it generally takes more instructions to do the same amount of work.

So what you are saying is that it specializes in particular instructions that it can run in one cycle and needs to run multiple of them if it needs to run something that is outside of that specialization.....................................but it's not specialized.

 

[Eximo]

So what you are saying is that it specializes in particular instructions that it can run in one cycle and needs to run multiple of them if it needs to run something that is outside of that specialization.....................................but it's not specialized.

No they are generalized compute instructions. And you need to chain many to accomplish the same goal that a CISC processor would have a single instruction for the same result.

 

[Pierce2623]

So what you are saying is that it specializes in particular instructions that it can run in one cycle and needs to run multiple of them if it needs to run something that is outside of that specialization.....................................but it's not specialized.

No it’s not “specialized” at all. It just runs instruction of a specific bit length, just like virtually every single other ISA in current use. X86 is actually the “specialized” stand out.