News TSMC 3nm Yield Problems May Derail AMD's CPU Plans

Oct 5, 2021
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Slow news day? Not loving the boy who cried wolf aspect of this story but it seems to be the norm lately.

The OP is super vague with no clarifying details on shipped units, process types, etc.

The newest TSMC N3 node advancement is EUV (ultraviolet). Announced end of Q3/21. Growing pains w a new node design aren't exactly uncommon. OP doesn't reference EUV in an article dated today. Apple and Intel are buying 3nm parts today.

So.. AMD and Nvidia still have options, imo.
 
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watzupken

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Doesnt this first affect apple? They use the newest process first. Like why is AMD first to be mentioned, click bait? Once apple is done with 3nm it should be perfect for amd.
It may affect AMD's roadmap, but I agree this is going to hit Apple and likely Intel hardest since they appear to be the biggest buyer of N3 at this point in time. Only companies will very deep pockets will meddle with cutting edge node. AMD most likely will stick with their next best advance node strategy.
 

renz496

Champion
Doesnt this first affect apple? They use the newest process first. Like why is AMD first to be mentioned, click bait? Once apple is done with 3nm it should be perfect for amd.
That's mean AMD and nvidia will be thrown under the bus by TSMC once again like what happen with 20nm. With 20nm TSMC end up giving 100% towards apple once it is hard for them for make 20nmHP process that needed by AMD and nvidia for their high end stuff. This end up forcing both AMD and nvidia sticking with 28nm. So we probably not going to reach a point where "things are iron out after apple use 3nm which allow AMD or nvidia to use the node for their product". Remember apple are not making 500mm2 (or bigger) type of chip that consume 300w or more.
 
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As for the supposed "3nm yield issues" rumored about by some anonymous sources in the article, there could potentially be some truth to them, but even if so, the suggestion that they "May Derail AMD's CPU Plans" is little more than baseless speculation, and is probably inaccurate. Keep in mind, AMD's current chiplet design is based entirely around making the best of low yields. It allows them to use a single compact chiplet across everything from entry-level CPUs to massive server processors. Is half of an 8-core chiplet defective? No problem, disable those cores and put it in a part utilizing four of them. The non-core portions of the processors are built on larger, established process nodes, and not as subject to yield issues. Needing to disable a portion of a large number of chiplets could potentially impact profits to some extent, but the markup they put on their current processors is quite large, giving them a lot of room to adjust for that while still being profitable. And from the sound of it, their upcoming GPU designs will also be moving to a similar multi-chip approach.

We are approaching a hard limit, as transistor features will never be smaller than 0 nm. Everyone will run into process issues at some point.
That's like stating that a microscope will never show features "smaller than 0 meters". You are effectively saying that things can't be smaller than an infinitely small size. : P

Of course things will continue to get harder to shrink the closer you get to the molecular limits of the materials, but it's probably also worth noting that the current "nm" ratings that are thrown around are more marketing numbers than anything, and the actual smallest features in a "3nm" chip will still be quite a bit larger than 3nm. I think it's been a couple decades since the process node names were an accurate measure of transistor gate sizes, and the actual transistor gate pitch for TSMC's current "5nm node" is somewhere around 48nm. So, it's likely they'll continue releasing marketing names for their nodes that imply feature sizes below 1nm within the next decade or so, even if that's not actually based on any real-world measurement. Of course, there is also likely still a lot of room for things like 3D chip design processes to improve efficiency and performance further even if the actual size of transistors isn't changing much. Along with improvements to the manufacturing process that could potentially reduce the cost per transistor without necessarily making them smaller.
 
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InvalidError

Titan
Moderator
I can distinctly remember people saying the same thing about sub-130nm lithography. "It's as small as light gets! It's a hard limit!"
130nm is only the limit for simple UV lithography.

The problem with 3nm is you cannot afford many out-of-place atoms when traces and other features are under 10 atoms wide. This is a hard physical limit, the practical minimum number of atoms necessary to make stuff work. At this point, chips failing due to atomic decay become a real concern.
 

Liquidrider

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Reports indicate that TSMC is struggling with 3nm process family yields; thus, some major PC industry customers like AMD and Nvidia might have to stick with 5nm technology longer than planned.

TSMC 3nm Yield Problems May Derail AMD's CPU Plans : Read more

This is going to affect Apple and Intel way way way way more than AMD. Do I really need to pull all the articles out about how Intel & Apple have been fighting over TSMC future 3nm supply. I mean my God Intel just mentioned as much at their investor day 3 days ago.

I'll be brutally honest. This was a completely shotty article. Substituting speculation over actual facts. Intel and Apple were mentioned once and practically as an after thought. 😑. If Intel is paying toms hardware for hit pieces at least try to look neutral.
 
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This is going to affect Apple and Intel way way way way more than AMD. Do I really need to pull all the articles out about how Intel & Apple have been fighting over TSMC future 3nm supply. I mean my God Intel just mentioned as much at their investor day 3 days ago.

I'll be brutally honest. This was a completely shotty article. Substituting speculation over actual facts. Intel and Apple were mentioned once and practically as an after thought. 😑. If Intel is paying toms hardware for hit pieces at least try to look neutral.
Intel needs tsmc 3nm but only for gpus, all their cpus are still on intel nodes, so intels cpu plans aren't derailing.

For apple it might be more of an issue but then again is apple even doing any x86 anymore? I don't think a lot of people here care about how arm production is going to be affected.

Also straight from the article:
" In addition, customers like Apple and Intel have paid a lot to secure N3 process chips in the coming months. Other partners like AMD must not have felt the urgency or need for such lavish pre-payments so that they will feel the most substantial effect of TSMC's yield issues. "

So yeah, AMD didn't pay up front so they have to wait.
 
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watzupken

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Intel needs tsmc 3nm but only for gpus, all their cpus are still on intel nodes, so intels cpu plans aren't derailing.

For apple it might be more of an issue but then again is apple even doing any x86 anymore? I don't think a lot of people here care about how arm production is going to be affected.

Also straight from the article:
" In addition, customers like Apple and Intel have paid a lot to secure N3 process chips in the coming months. Other partners like AMD must not have felt the urgency or need for such lavish pre-payments so that they will feel the most substantial effect of TSMC's yield issues. "

So yeah, AMD didn't pay up front so they have to wait.
It will be hard to tell what Intel is going to use the fab allocation for. At this point, I agree it is likely going to be GPUs, but till they managed to deploy their 5nm (actual 5nm, not some fancy 1.8nm naming), we won't know if they may use TSMC's 3nm when the competition gets too hot.
The likes of AMD generally go with the second best advance node, and not the cutting edge ones because they don't have such deep pockets. So it is possible that they may end up with some interim node like N4 or N5+, whatever they want to call it.
 
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Oct 7, 2021
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130nm is only the limit for simple UV lithography.

The problem with 3nm is you cannot afford many out-of-place atoms when traces and other features are under 10 atoms wide. This is a hard physical limit, the practical minimum number of atoms necessary to make stuff work. At this point, chips failing due to atomic decay become a real concern.
3nm is for sure approaching the limits of known physics, but these are all marketing terms. TSMC 3nm is not literally 3nm in size, so we still have quite a while to go before that becomes an issue.
 
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Oct 7, 2021
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The rumors last year had Intel producing a few GPU and enterprise CPU's on 3nm from TSMC.

https://www.notebookcheck.net/TSMC-will-manufacture-some-of-Intel-s-3nm-hardware-starting-in-July-2022.554888.0.html
Intel's Meteorlake in H1 2023 is chiplet design, using TSMC 3nm for the iGPU, and Intel 4 for the rest of the chip. If Intel can't get the supply of N3 needed, then either they delay MeteorLake, or drastically reduce the iGPU performance - Which, idk is worse. My understanding from their recent investors meeting was that the N3 based iGPU module was going to be primarily in mobile chips to try and compete with Apple and AMD heavily in mobile GPU performance without needing a discreet chip. This delay shouldn't effect desktop too much, or most Xeon's ( I believe only 2 or 3 Xeon SKUs were planned for N3, while the rest on Intel 7 for 2023)
 
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Oct 7, 2021
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As for the supposed "3nm yield issues" rumored about by some anonymous sources in the article, there could potentially be some truth to them, but even if so, the suggestion that they "May Derail AMD's CPU Plans" is little more than baseless speculation, and is probably inaccurate. Keep in mind, AMD's current chiplet design is based entirely around making the best of low yields. It allows them to use a single compact chiplet across everything from entry-level CPUs to massive server processors. Is half of an 8-core chiplet defective? No problem, disable those cores and put it in a part utilizing four of them. The non-core portions of the processors are built on larger, established process nodes, and not as subject to yield issues. Needing to disable a portion of a large number of chiplets could potentially impact profits to some extent, but the markup they put on their current processors is quite large, giving them a lot of room to adjust for that while still being profitable. And from the sound of it, their upcoming GPU designs will also be moving to a similar multi-chip approach.


That's like stating that a microscope will never show features "smaller than 0 meters". You are effectively saying that things can't be smaller than an infinitely small size. : P

Of course things will continue to get harder to shrink the closer you get to the molecular limits of the materials, but it's probably also worth noting that the current "nm" ratings that are thrown around are more marketing numbers than anything, and the actual smallest features in a "3nm" chip will still be quite a bit larger than 3nm. I think it's been a couple decades since the process node names were an accurate measure of transistor gate sizes, and the actual transistor gate pitch for TSMC's current "5nm node" is somewhere around 48nm. So, it's likely they'll continue releasing marketing names for their nodes that imply feature sizes below 1nm within the next decade or so, even if that's not actually based on any real-world measurement. Of course, there is also likely still a lot of room for things like 3D chip design processes to improve efficiency and performance further even if the actual size of transistors isn't changing much. Along with improvements to the manufacturing process that could potentially reduce the cost per transistor without necessarily making them smaller.
I agree with most of what you said, but AMD's chiplet design doesn't necessarily mean it makes N3, in it's current state, profitable to use. Low yields = higher costs. Greymon55's leak seem like the most likely scenario - AMD will either postpone Zen5 until N3 yields improve, releasing a Zen4+ on N4 in the meantime, or backport Zen5 to N4.
 
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InvalidError

Titan
Moderator
3nm is for sure approaching the limits of known physics, but these are all marketing terms. TSMC 3nm is not literally 3nm in size, so we still have quite a while to go before that becomes an issue.
It isn't all marketing, part of it is still grounded in physical feature sizes and some features are smaller than the node name suggests. For example: Intel's 14nm FinFET fins are actually only 8nm wide.

The marketing aspect is in how the feature sizes get weighed to decide the name based on overall density scaling.
 
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hannibal

Distinguished
When the 3nm is not even near 3nm... We are not hitting wall... 3nm is most likely neat 30nm in reality most likely larger than that. We allways has to remember that marketing nm is not the same as real nm...
Yeah there are some part that are not so far from the marketed nm... but even that Intel 14nm vs 8nm is quite big and when considering that intel 14nm is something like 40 to 50 nm in reality in most parts... Yeah, it is still valid to say what the real size is and what it is not.
 
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jkflipflop98

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130nm is only the limit for simple UV lithography.

The problem with 3nm is you cannot afford many out-of-place atoms when traces and other features are under 10 atoms wide. This is a hard physical limit, the practical minimum number of atoms necessary to make stuff work. At this point, chips failing due to atomic decay become a real concern.
I'm not sure why you quoted me for this random nugget of trivia. But thanks.
 

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