so is it their 3nm or 2nm that is comparable?
"
TSMC: Our 3nm Node Comparable to Intel's 1.8nm Tech
By
Anton Shilov
published about 8 hours ago
TSMC believes its
2nm technology will beat Intel's 1.8nm-class process."
or is this the whole node vs nanometer naming circus?
Dear Anton Shilov,
Please don't change your heading because there are analyst out there want to limited it's lost.
C. C. Wei - Taiwan Semiconductor Manufacturing Company Limited - CEO
Well, Gokul, this is C. C. Wei. Let me answer your question with a very simple answer is that no, but what I will state a little bit long. Actually, we do not underestimate any of our competitors or take them lightly. Having said that, our internal assessment shows that our N3P,
now I repeat again,N3P technology, demonstrated comparable PPA to 18A, my competitor's technology, but with an earlier time to market, better technology maturity, and much better cost. In fact, let me repeat again, our 2-nanometer technology without backside power is more advanced than both N3P and 18A and will be semiconductor industry's most advanced technology when it is introduced in 2025. Does that answer your question, Gokul?
Don't let media trying to white washing what is happened. This is a foolish comment from a CEO of a multi billion dollar company. This foolishness needed to be recorded.
I see the article has now corrected the title and now says that TSMC claims that their
2nm class node (and NOT their 3nm as incorrectly written initially) will beat Intel’s 18A (1.8nm). The forum title is still wrong though. Anyway TSMC saying that their 2nm node is better (in some metric) is more believable than saying that their already existing FINFET 3nm node (which is a failure by the way – at least for the time being) is better than Intel’s 18A (which is based on GAAFET/RibbonFET).
Intel’s 18A is a revision of their 20A process (i.e. their 2nm class node). It is not a truly new node in the classical density doubling sense. Instead it is similar to how TSMC went from ‘20nm’ to ‘16nm’ or from ‘16nm’ to ‘12nm’ or from ‘7nm’ to ‘6nm’ or from ‘5nm’ to ‘4nm’. When Intel renamed their nodes to align with TSMC it decided to follow TSMC’s philosophy of claiming a new node not on the basis of doubling of transistor density but on the basis of improving performance per watt (which is the other characteristic being improved by moving to a new node). A typical node shrink (one that doubles the density) would typically achieve 20-30% better performance per watt so whenever that was achieved (alongside sometimes some modest improvement in density (5-15%)) TSMC and Samsung were claiming a new node. So Intel decided to follow suit. Had Intel not gone through the rabbit hole of following TSMC’s and Samsung’s naming shenanigans and continued to name their nodes solely based on density you would have:
| Intel 7 | 10nm+++ |
| Intel 4 | 7nm |
| Intel 3 | 7nm++ |
| Intel 20A | 5nm |
| Intel 18A | 5nm++ |
It is likely that in some metric TSMC’s 2nm class node (which will come in three variants N2, N2P and N2X) might beat 18A. That’s not the first time something like that would happen. Right now Intel can claim that their Intel 7 (‘7nm class’ when aligned to TSMC’s naming) is better than TSMC’s N7/N7P (7nm), N6 (6nm), N5 (5nm), N4 (4nm) and N3 (3nm) nodes in terms of transistor performance as it can manufacture cpus that can clock to higher frequencies than cpus manufactured at any of these TSMC’s nodes. It can even claim higher performance per watt at those very high frequencies. In any case it depends on the metric that TSMC will claim such a ‘win’ over 18A.
If you are talking about this again then TSMC N2 is just TSMC N5+++++ (which is 7nm)
Uh oh... You don't know that D1, or any other Intel fab on the planet (except Fab 34 in Ireland), doesn't have EUV HVM capacity.
Fab 34 just recently received enough EUV tools required to produce Intel 4 wafers.
A few EUV tools here and there can only make low yield prototypes at best.
You clearly don't have a clue as to how many EUV tools are required for HVM of SoC complexity wafers.
By the end of 2023 Intel will only have less than 25 EUV tools, whereas TSMC will have over 125.
How many interconnect layer is Intel 4, because it is the first time it use EUV unlike TSMC, we can believed that not all 16 layers is done in EUV, looking at the chart below, (although pitch is only a indicator), the case is that might be intel only needed to use EUV in M0, but, let say there is a higher increase between M4 to M5 layer, therefore it is an educated guess that M0-M4 EUV layer the rest is DUV layer.
According to a number of site, Meteor CPU chiplet is smallest, and the fact that out of the 16 layers only 5 needed EUV so to have only Intel D1 to have EUV machine in itself is enough to put out Meteor Lake Laptop only volume, I think ASML is slow to produce the machine, (i.e. there was a fire) but I am not going to give the benefit and say it is totally the management fault, but to focus on the most valuable segment and keep Intel 4 going as it should be, as a shareholder, I think I am Ok with this.
Be Honest, TSMC is non-investment grade because it's CEO can say things never should come out of his month. If you are in trouble, admin it, come with a plan, not going out to say lies which to an educated person is just an insult.
xcx
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