News TSMC Preps for 3nm Risk Production

[Admin]

TSMC ups CapEx budget significantly as it preps for additional Apple & Intel orders

TSMC Preps for 3nm Risk Production : Read more

 

[Co BIY]

Very interesting article.

Please define "Risk Production" for those of us less savvy.

 

[jkflipflop98]

They're basically saying that they think they know how to build the layers, and they're going to start trying to run some wafers through the entire process line.

 

[Uniblab]

They're basically saying that they think they know how to build the layers, and they're going to start trying to run some wafers through the entire process line.

Seriously suprised that intel has fallen behind as they were process node leading up until they hit some kind of barrier around 10nm. 3nm is where <if I remember correctly>, is where the actual atomic structure becomes a barrier. Cant logically make a transistor smaller than the atom itself. Or can they? I am still suprised that it takes soo much to go soo small and as far as I know there is only one fab machine manufacturer that is making the machines that can go so small. Deep UV is only made by ASML, so that kinda restricts it to the fabs that are already capable to accept the tooling. New Fab? 100 million per toolset? Wonder how long before TSMC will have any appreciable competition in that field. If intel is laying behind the bushes - I dont think they make their own tooling - only TSMC will be able to go so small. The booming business of making things smaller.

 

[spongiemaster]

Very interesting article.

Please define "Risk Production" for those of us less savvy.

Here's a link which explains it in a bit more detail.

https://www.edn.com/tsmc-risk-production-what-does-it-mean-for-28nm/

3nm is where <if I remember correctly>, is where the actual atomic structure becomes a barrier. Cant logically make a transistor smaller than the atom itself.

3nm is just a marketing term and is not the gate length that it originally represented. The gate length of Intel's 10nm process is 18nm and Intel's 10nm is roughly equivalent to TSMC's and Samsung's 7nm in transistor density, so their labels are even further from the truth.

 

[jkflipflop98]

Seriously suprised that intel has fallen behind as they were process node leading up until they hit some kind of barrier around 10nm. 3nm is where <if I remember correctly>, is where the actual atomic structure becomes a barrier. Cant logically make a transistor smaller than the atom itself. Or can they? I am still suprised that it takes soo much to go soo small and as far as I know there is only one fab machine manufacturer that is making the machines that can go so small. Deep UV is only made by ASML, so that kinda restricts it to the fabs that are already capable to accept the tooling. New Fab? 100 million per toolset? Wonder how long before TSMC will have any appreciable competition in that field. If intel is laying behind the bushes - I dont think they make their own tooling - only TSMC will be able to go so small. The booming business of making things smaller.

You have to remember, this "3nm" node isn't actually 3nm. They might be able to get a 3nm line width at the contact/M0 layer, but that's about it. 3nm is just a marketing term.