News TSMC Readies N2P and N2X: 2nm with Enhanced Performance

TSVs must have gotten really cheap if TSMC can now afford to feed transistors from the backside.

The signal side of things is still going to require some ground and power planes to carry high-speed return currents and provide whatever rails aren't being shoved up the backside.

Imagine if the IHS actually became active DC ground carrying about half of peak load. All of the ground rail vias going through the die to the IHS should reduce the silicon slab's net thermal resistance too.
 
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I know nothing about semiconductor processing but:
There are no planes in an IC unless these are planes added above the signal metallization layers. Everything is powered by rails. Instead of supplying these rails powered from the power ring around the periphery of the IC, these rails are fed through vias to the back side of the IC. This would require thousands or millions, not billions of connections through the IC. To put things in perspective many cameras use back side imaging where there is one via or via set per pixel going through the die allowing for millions of connections.

To get this to work, the die must be made very thin. This thinness will help quiet a bit with heat transfer.
This process will be far from free.
 
We already thin wafers through a backside grind process. If you imagine the edge of a wafer, and then zoom in so that the thin edge of the wafer is 10 feet tall, we only use the top two inches of the wafer. The rest of the wafer's thickness is there for structural stability during fabrication.
 
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