News TSMC says it doesn't care if Moore's Law is alive or dead if technology keeps scaling — 3D chip packaging fuels continued advances

[Admin]

TSMC's Kevin Zhang states that while Moore's Law's traditional focus on transistor density may be less relevant, TSMC's continual advancements in technology scaling and 2.5D and 3D integration make it more than alive.

TSMC says it doesn't care if Moore's Law is alive or dead if technology keeps scaling — 3D chip packaging fuels continued advances : Read more

 

[bit_user]

For about a decade, Apple has been TSMC’s alpha customer, which is why the evolution of TSMC’s process technologies is very well described by the evolution of Apple's processors.

If you look at their M-series, the M1 (Nov 2020) and M2 (June 2022) both used TMSC N5. Meanwhile, the Snapdragon 8 Gen 2 launched a few months later on TSMC N4P. Apple didn't recover the lead until the Oct. 2023 launch of the M3.

when you examine TSMC’s capabilities beyond Apple’s processors, you will note AMD’s Instinct MI300X and Instinct MI300A processors with AI and HPC capabilities.

Well, Apple made the M1 Ultra with two compute dies + 2.5 TB/s link + 16 stacks of LPDDR5. I guess the point might be that Apple hasn't yet delved into die-stacking, other than using stacked DRAM.

I think this next part is most telling:

“[Observers] narrowly defined Moore’s Law based on two-dimensional scaling—that is no longer the case,” Zhang said. "As you look at the innovation hype in our industry, we actually continue to find different ways to integrate more functions and capabilities into smaller form factors. We continue to achieve a higher level of performance and a higher level of power efficiency. So from that perspective, I think that Moore’s Law, or technology scaling, will continue.”

He's just focusing on density-scaling! While that drives performance, cost-scaling is a very close second priority for most of us! 3D stacking means fabbing more chips + additional assembly costs. All of that is great, if you're the one fabbing/assembling the chips, but it doesn't address an increasingly dominant factor in the deceleration of real world performance gains for all but the most deep-pocketed customers.

Here's an old chart, but it illustrates the point quite nicely. If anyone knows of a more recent cost-scaling analysis, please share!

Source: https://www.quora.com/How-does-the-number-of-transistors-per-chip-increase-according-to-Moore-s-law
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[waltc3]

Moore's Law: marketing guff, generally used to help consumers conceptualize something that stretches the limits of their technical comprehension. It also helps them feel more secure when discussing tech with other n00bs...😉 I agree with the TSMC CEO, because the nonexistent law, Moore's Law, is not something that CPU designers target. Nobody scraps a design because, "It's not Moore's Law compliant--fail"...😉

 

[bit_user]

Moore's Law: marketing guff,

I think it's most helpfully cited as convention, rather than a law. There's no physical law which dictated that rate of density increase. It just reflected a rate of improvement that was relatively comfortable and practical for the industry to follow, over the course of several decades.

Does that mean the industry could've improved faster than Moore's Law? Probably, but at what cost? Trial-and-error is an underappreciated feature of many engineering endeavors, and the consequences of being too ambitious in the objectives of a single generation is possibly best exemplified in the historic delays that beset Intel's infamous 10 nm node. Lately, it seems those delays might not be the only casualty, given that Raptor Lake is made on a node that's still basically an iteration of that same 10 nm process (in spite of branding it "Intel 7").

By contrast, TSMC continued to move much more incrementally. That consistent progress eventually overtook Intel.

 

[A Stoner]

"TSMC highlighted that the foundry’s transitions from 5nm to 3nm-class process nodes result in PPA improvements exceeding 30% per generation."

This is where they really need to start using a different metric than Xnm or soon-to-be A angstroms.

5nm to 3nm should be a 64% area improvement, but here they are using PPA which should be a much larger improvement and only getting 30%.

 

[bit_user]

"TSMC highlighted that the foundry’s transitions from 5nm to 3nm-class process nodes result in PPA improvements exceeding 30% per generation."

This is where they really need to start using a different metric than Xnm or soon-to-be A angstroms.

5nm to 3nm should be a 64% area improvement, but here they are using PPA which should be a much larger improvement and only getting 30%.

PPA != density, though. I suppose that's what you meant by your last sentence?

Maybe someone with actual knowledge can shed some light onto this, but when someone like TSMC shares PPA (Performance Per Area) numbers, do they mean just the effect of the maximum clockspeed increase you'd get from fabbing the same design on the new node? Is that at iso-power or just like max vs. max?

 

[passivecool]

Moor's 'Law' = Schrödinger's cat

If you like i can get gpt to write a compelling case to support this thesis.

 

[A Stoner]

PPA != density, though. I suppose that's what you meant by your last sentence?

Maybe someone with actual knowledge can shed some light onto this, but when someone like TSMC shares PPA (Performance Per Area) numbers, do they mean just the effect of the maximum clockspeed increase you'd get from fabbing the same design on the new node? Is that at iso-power or just like max vs. max?

PPA = performance, power, and area. So, a 90% reduction in power use and a doubling of area keeping performance the same would equate to and 80% improvement in PPA.

I am mostly complaining about the node size statements they make... If the process goes from 10 nm to 5 nm, this a not an arbitrary statement. Sizes are objective, not subjective. That is really what my complaint is.

PPA is a reasonable approximation of process node efficiency and maybe they could use that instead of the fake sizing.

Honestly, other than a few niche items, no one truly cares about the area, they really only care about the performance and the power.

 

[bit_user]

Honestly, other than a few niche items, no one truly cares about the area, they really only care about the performance and the power.

Area is interesting for making cost projections. People sometimes deduce wafer pricing (or find leaks about it). If you know density projections, you can compute how many dies containing a certain number of cores of a given design are able to fit per wafer, and that can give you a rough cost estimate per die.

Also, knowing density and die size, one can estimate transistor count. This can be used as a rough metric to compare the relative complexity of different products, although it's a very rough estimate, with lots of assumptions built in.

Those are all just matters of interest to the armchair analyst. I agree that consumers don't care about area, itself. They care about power, performance, and price. Then again, such articles aren't aimed at end consumers, so I think it's fair game to go further in depth.