News TSMC Starts $19.5 Billion 3nm Fab Construction

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I am certainly spitballing but from what I know of quantum physics getting a true stable 3nm transistor is impossible with conventional silicon. Is anyone knowledgable enough to explain this to me and others?

*Edit: I found some information:
“In a finFET technology, the width of the device is quantized. You can have one fin, two fins, three fins or whatever. In nanosheets, you have a fixed number of nanosheets on top of each other. But you can play with the width. Now, you have access to a continuum of device widths, which you didn’t have for the finFET,” Mocuta said. “For example, you want to have an area that drives a lot of current. That could be a buffer. Then, you want to have an SRAM with a very small footprint. There are different needs on the chip that can be met.”

Source:https://semiengineering.com/big-trouble-at-3nm/
 
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