News TSMC tandem builds exotic new memory with radically lower latency and power consumption — MRAM-Based memory can also conduct its own compute operat...

[Admin]

TSMC and ITRI to jointly develop ultra-low-power spin-orbit-torque magnetic random-access memory.

TSMC tandem builds exotic new memory with radically lower latency and power consumption — MRAM-Based memory can also conduct its own compute operat... : Read more

 

[usertests]

SOT-MRAM is theoretically capable of latencies up to 10ns, which is certainly slower compared to SRAM (read and write latency of SRAM is typically in the range of 1-2ns), but is slightly faster than DRAM (DDR5 has latency around 14ms) and considerably faster than 3D TLC NAND (which has read latencies between 50 and 100 microseconds).

DRAM = 14 nanoseconds (not milliseconds). The rest look fine.

 

[George³]

Zero words about capacity and possible prices.

 

[user42]

DRAM = 14 nanoseconds (not milliseconds). The rest look fine.

That makes WAY more sense! 14ms is nearly forever compared to 10-14ns.

 

[bit_user]

DRAM = 14 nanoseconds (not milliseconds).

I wonder where that number is from. I think the best we've seen in PC benchmarks is somewhere in the realm of 70 ns.

The rest look fine.

Uh, not NAND.

3D TLC NAND (which has read latencies between 50 and 100 microseconds)

Not according to this:

​

That's 11-15 microseconds from the time a CPU sends a read request to the SSD's controller, and when it receives back 4 kiB of data. So, the raw latency of 3D TLC NAND is definitely in the lower single digit numbers of microseconds, if that.

 

[TJ Hooker]

I wonder where that number is from. I think the best we've seen in PC benchmarks is somewhere in the realm of 70 ns.

If I had to guess, maybe from CAS latency at JEDEC standard timings? It's usually around 14-16 ns.

 

[bit_user]

If I had to guess, maybe from CAS latency at JEDEC standard timings? It's usually around 14-16 ns.

But that's not a full access (CAS = Column Address Strobe), right? To provide comparable figures, you want to look at the amount of time for a random access to get the actual data.

 

[thestryker]

MRAM has been the next big thing for like 40 years so I'll believe it when it gets into a production unit.

 

[TJ Hooker]

But that's not a full access (CAS = Column Address Strobe), right? To provide comparable figures, you want to look at the amount of time for a random access to get the actual data.

Oh, yeah, I don't think using CL provides an apples to apples comparison, just speculating on where the number may have come from.

 

[d0x360]

"jointly developed co-developed a spin-orbit-torque magnetic random-access memory (SOT-MRAM) array chip, the result of a joint development"

So you're saying it was developed in cooperation with another company?

Seriously who wrote this? So from 4 years ago? A single CO developed there is no hyphen btw, would have been sufficient but this sounds like it was written by a 5th grader who doesn't understand what they are saying.

 

[subspruce]

DRAM = 14 nanoseconds (not milliseconds). The rest look fine.

DRAM latencies used to go down to 6ns in the DDR3 days.

 

[usertests]

DRAM latencies used to go down to 6ns in the DDR3 days.

Three ways to fix DRAM's latency problem

DRAM has been powering computer memory for some 50 years, but there's a problem. While DRAM capacities have grown, and bandwidth has too, latency has barely changed in the last two decades. Here's three ways to fix that.

www.zdnet.com

It's a problem they always have to fend off, it seems. And it will probably continue to get worse with further density increases and the introduction of 3D DRAM for consumers.

 

[bit_user]

Three ways to fix DRAM's latency problem

DRAM has been powering computer memory for some 50 years, but there's a problem. While DRAM capacities have grown, and bandwidth has too, latency has barely changed in the last two decades. Here's three ways to fix that.

www.zdnet.com

That article is a little sketchy. Their first suggestion is essentially what HBM does. However, HBM has slightly worse latency than normally-connected DRAM. Their second suggestion is to change the refresh architecture, but I'm very skeptical just how much real-world impact refreshes have on DRAM latency - I think it's tweaking at the margins, at best. I do appreciate that their final suggestion affixes a specific claim of 13% to 20% reduction, based on topology improvements.

Anyway, the article is from 2017 and therefore has limited relevance to DDR5.

It's a problem they always have to fend off, it seems. And it will probably continue to get worse with further density increases and the introduction of 3D DRAM for consumers.

Don't forget how DDR5 adds on-die ECC. That will add a couple nanoseconds, based on my rough estimates of the logic complexity.

LPDDR5 makes it even worse, based on how certain operations are multiplexed between the memory controller and DRAM.

I think having much closer coupling of processing & DRAM could be a game changer. Instead of having the CPU's memory controller talking to interface circuitry on the DRAM dies, you can blur the lines and have the memory controller accessing DRAM contents much more directly.