News TSMC to Adopt High-NA EUV Tools in 2030 or Later: Report

[Admin]

According to China Renaissance, TSMC might adopt High-NA EUV lithography for a post-1nm process technology in 2030 or later.

TSMC to Adopt High-NA EUV Tools in 2030 or Later: Report : Read more

 

[thestryker]

If they're talking ready for production in 2030 I could almost buy into that, but if they're talking not acquiring until then that doesn't seem likely. I don't think relying on Apple to subsidize all of their new nodes is a viable strategy with Intel being as aggressive as they are. It's not unreasonable to believe that Intel could be competing 1:1 and be able to offer an equivalent node for less money by 2030.

 

[Co BIY]

TSMC may also be looking at the availability of machines and wants to avoid a bidding war with Intel that would only benefit ASML.

If they think they have a lot of mileage left in their current processes I can see this as a smart conservative strategy.

 

[hannibal]

TSMC may also be looking at the availability of machines and wants to avoid a bidding war with Intel that would only benefit ASML.

If they think they have a lot of mileage left in their current processes I can see this as a smart conservative strategy.

Sounds sensible. New smaller nodes are nice, but not at any cost…

 

[gg83]

Has Intel always adopted the latest machines from asml first? Do we know who is likely to buy intels first gen of they're latest nodes? Is it government?

 

[bit_user]

Has Intel always adopted the latest machines from asml first?

No. TSMC was first to adopt EUV.

It was previously reported that Intel co-developed high-NA in partnership with ASML. I think this gave Intel a window of exclusivity.

Do we know who is likely to buy intels first gen of they're latest nodes? Is it government?

Huh? Which nodes? They have made some announcements of different commercial customers lined up to use some of their nodes, but I haven't been keeping track. I don't recall hearing about any government (contractor) customers, but I'm not sure if those would be announced.

It does raise an interesting question of what chips & nodes might be getting eyed/used for things like autonomous weapons. They can't go with mil-spec parts, because those simply lack the compute density & power efficiency. So, they must be looking at/using fairly cutting-edge nodes. That brings us to the next question of what sort of architecture these chips have. Do they just license some DSP cores from Cadence, Synopsis, etc. and fab a big die with some HBM around it? Who even are the big chip contractors who might do it?

 

[phead128]

It's not unreasonable to believe that Intel could be competing 1:1 and be able to offer an equivalent node for less money by 2030.

Intel has access to the same EUV tools that TSMC has all this time. If they could match 1:1 to TSMC, they should prove it with existing nodes.

 

[thestryker]

Intel has access to the same EUV tools that TSMC has all this time. If they could match 1:1 to TSMC, they should prove it with existing nodes.

Nothing you've said here makes any sense at all. Maybe you just don't know about how the fabrication industry has operated?

Intel opted to move forward with 10nm (which has similar density to TSMC N7, and originally. was supposed to be even more) on DUV which means they bought no EUV machines until years after TSMC did. Based on what public information is available Intel 7 costs more than Intel 4 due to a the hoops required to use DUV.

They've gotten EUV machines and are putting them to use with Intel 4 for MTL right now with Intel 3 and 20A later this year which should get them to parity with TSMC. They won't be any cheaper than TSMC and if using RibbonFET and PowerVia they will be more expensive since they're using the same equipment.

They're installing High-NA now to get a jump on learning to implement usage and should be aimed at post 18A nodes though High-NA machines should be able to process more wafers than existing EUV machines.

ASML has been backlogged on EUV machines since they were introduced and High-NA is even worse. Intel has chosen to move forward quickly to maximize their fabrication throughput while ensuring they can minimize costs.

 

[gg83]

No. TSMC was first to adopt EUV.

It was previously reported that Intel co-developed high-NA in partnership with ASML. I think this gave Intel a window of exclusivity.


Huh? Which nodes? They have made some announcements of different commercial customers lined up to use some of their nodes, but I haven't been keeping track. I don't recall hearing about any government (contractor) customers, but I'm not sure if those would be announced.

It does raise an interesting question of what chips & nodes might be getting eyed/used for things like autonomous weapons. They can't go with mil-spec parts, because those simply lack the compute density & power efficiency. So, they must be looking at/using fairly cutting-edge nodes. That brings us to the next question of what sort of architecture these chips have. Do they just license some DSP cores from Cadence, Synopsis, etc. and fab a big die with some HBM around it? Who even are the big chip contractors who might

No. TSMC was first to adopt EUV.

It was previously reported that Intel co-developed high-NA in partnership with ASML. I think this gave Intel a window of exclusivity.


Huh? Which nodes? They have made some announcements of different commercial customers lined up to use some of their nodes, but I haven't been keeping track. I don't recall hearing about any government (contractor) customers, but I'm not sure if those would be announced.

It does raise an interesting question of what chips & nodes might be getting eyed/used for things like autonomous weapons. They can't go with mil-spec parts, because those simply lack the compute density & power efficiency. So, they must be looking at/using fairly cutting-edge nodes. That brings us to the next question of what sort of architecture these chips have. Do they just license some DSP cores from Cadence, Synopsis, etc. and fab a big die with some HBM around it? Who even are the big chip contractors who might do it?

I found an article from 2022 stating all the latest AI- enabled chips are exclusively coming from TSMC plants in Taiwan. I'm interested now. I'll try do find out what happens after the wafer is made.

 

[ToBeGood]

Sounds sensible. New smaller nodes are nice, but not at any cost…

Sound totally non-sense.

The real reason why TSMC fire its Chair is not because of US FAB, this delay is the No1 reason why he is sacked.

https://www.cnbc.com/2022/03/23/ins...anced-chipmakers-use-for-euv-lithography.html

If TSMC N3B can have good yield and not leading to N3E reduced double patterning and increase in size (i.e. N3B is better than N3E (going backward)).

A third grade can do the maths i.e. you +- double the amount of cost i.e. 2 Vs 1 exposure and the cost of the machine is 200M Vs 300M, so EUV high NA increase 50% but it reduced the exposure cost by 100% so that is a 50% cost gain by switching to the new machine, and on top of that EUV High NA reduced the risk of reducing yield cause by mis-algin double patterning.

You call this sensible please do your math because yada yeda yeda fanboy.

 

[cyrusfox]

If TSMC N3B can have good yield and not leading to N3E reduced double patterning and increase in size (i.e. N3B is better than N3E (going backward)).

A third grade can do the maths i.e. you +- double the amount of cost i.e. 2 Vs 1 exposure and the cost of the machine is 200M Vs 300M, so EUV high NA increase 50% but it reduced the exposure cost by 100% so that is a 50% cost gain by switching to the new machine, and on top of that EUV High NA reduced the risk of reducing yield cause by mis-algin double patterning.

You call this sensible please do your math because yada yeda yeda fanboy.

Double patterning does not require double exposure... Only if you need to rework, and that is the same for any litho step whether pattern multiplication processes are used or not.

The higher cost comes from the subsequent processing needed to reduce the line feature size (Etch/trim, oxide dep, etch/resist clean, and final etch/dep)

The increased processing adds additional complexity (Defects and margin for error). But does not increase Litho tool utilization or need for additional exposure. The design is a bit trickier in terms of routing, but vias and inventive design can solve that.

As for TSMC strategy whether disputed now or not seems to be the course they are on. A supportive point to their strategy is everyone(Memory makers, Samsung, TSMC, Global, Intel, etc) was able to progress with DUV past 39nm(limit of DUV) with these tricks for nearly a decade, When TSMC is at the wall of what EUV can accomplish without patterning tricks, there should still be plenty of mileage to get them another 4-5 years, and it might be the cost optimized route with how out of hand Litho BOM has became in Semiconductor Fabrication. Although it may give Intel the lead again in node advancement(Intel should have an easier way of achieving smaller features and do so faster), but at what price?

 

[ToBeGood]

Double patterning does not require double exposure... Only if you need to rework, and that is the same for any litho step whether pattern multiplication processes are used or not.

The higher cost comes from the subsequent processing needed to reduce the line feature size (Etch/trim, oxide dep, etch/resist clean, and final etch/dep)

The increased processing adds additional complexity (Defects and margin for error). But does not increase Litho tool utilization or need for additional exposure. The design is a bit trickier in terms of routing, but vias and inventive design can solve that.

As for TSMC strategy whether disputed now or not seems to be the course they are on. A supportive point to their strategy is everyone(Memory makers, Samsung, TSMC, Global, Intel, etc) was able to progress with DUV past 39nm(limit of DUV) with these tricks for nearly a decade, When TSMC is at the wall of what EUV can accomplish without patterning tricks, there should still be plenty of mileage to get them another 4-5 years, and it might be the cost optimized route with how out of hand Litho BOM has became in Semiconductor Fabrication. Although it may give Intel the lead again in node advancement(Intel should have an easier way of achieving smaller features and do so faster), but at what price?

What are you talking about ????

Fill/Cut Self-Aligned Double-Patterning

Explaining cut masks and how to comply with a variety of different rules.

semiengineering.com

"while SADP generates the pitch (mask) split using spacers that are self-aligned to the first litho-etch step. The second mask in an SADP process is a block or cut mask used to trim the tips of the lines created in the first step and/or remove dummy lines."

The keyword in the above quote is "The Second Mask", you can have all the automation in the world and the exposure is done is an automated manner (looks like it is one step), I am old and my father have a camera shop, so I have a lot of broken camera to play with, so it is natural to me, how many times to camera shutter open then count as how many exposure, you have 2 mask i.e. the camera door open 2 times, so 2 exposures.

Don't make me sound like a fool, I also worked for Hoya before (one of the leading mask company), because the more you are the more it make you are the fool.

The fact is that EUV is a very weak light source, the early problem of EUV machine it's it through put, there are 2 times camera shutter opens so the through put of the EUV light source is effectively reduced. period.

 

[cyrusfox]

What are you talking about ????

Fill/Cut Self-Aligned Double-Patterning

Explaining cut masks and how to comply with a variety of different rules.

semiengineering.com

"while SADP generates the pitch (mask) split using spacers that are self-aligned to the first litho-etch step. The second mask in an SADP process is a block or cut mask used to trim the tips of the lines created in the first step and/or remove dummy lines."

The keyword in the above quote is "The Second Mask", you can have all the automation in the world and the exposure is done is an automated manner (looks like it is one step), I am old and my father have a camera shop, so I have a lot of broken camera to play with, so it is natural to me, how many times to camera shutter open then count as how many exposure, you have 2 mask i.e. the camera door open 2 times, so 2 exposures.

Don't make me sound like a fool, I also worked for Hoya before (one of the leading mask company), because the more you are the more it make you are the fool.

The fact is that EUV is a very weak light source, the early problem of EUV machine it's it through put, there are 2 times camera shutter opens so the through put of the EUV light source is effectively reduced. period.

The double pattern itself is only the second mask, that is the only item being patterned at high density.
https://en.wikipedia.org/wiki/Multiple_patterning#Spacer-is-dielectric_(SID)_SADP

You can do the preliminary mask at a much cheaper DUV litho tool. The economics will likely still work to TSMC favor, that is my point, and pattern multiplication is well established already, they don't need to reinvent that wheel.