News Ventana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo

[Admin]

Ventana's Veryon V2 chip is built on RISC-V, offers up to 192 cores, and offers custom chiplets with hardware acceleration.

Ventana's 192-Core RISC-V CPU Takes Aim At AMD Epyc Genoa And Bergamo : Read more

 

[Amdlova]

Intel will show somenthing with risc V...
The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...

 

[atomicWAR]

I have found Intel's interest in Risc V as rather eye opening. I can only assume they have either big plans with it or want to make sure they can counter it with x86.

Intel will show somenthing with risc V...
The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...

This would be neat to see but with the difference in their instruction sets I imagine some type of translation layer or emulation would need to happen unless OSes and apps directly incorporated them. Something I find unlikely but not impossible. Regardless unless they are running native code as you know emulation/translation layers slow said CPUs performance. Time will tell and I am certainly interested to see how things shake out.

 

[sygreenblum]

I have found Intel's interest in Risc V as rather eye opening. I can only assume they have either big plans with it or want to make sure they can counter it with x86.

This would be neat to see but with the difference in their instruction sets I imagine some type of translation layer or emulation would need to happen unless OSes and apps directed incorporated them. Something I find unlikely but not impossible. Regardless unless they are running native code as you know emulation/translation layers slow said CPUs performance. Time will tell and I am certainly interested to see how things shake out.

It's possible but yuck. Reminds me of Transmeta. Given Apple did a better job when they transitioned to the arm instruction set but they have control of the whole ecosystem and even then it wasn't without its problems and was always a good deal slower than native. I don't think this is Intel's plan.

I don't know what Intel has planned with Risc V but my assumption was they'd start with infrastructure products like data center switches and routers, set-top/CMTS, cable modems, and PON/DSL, Ethernet NICs, filters and amplifiers, wireless connectivity solutions, embedded processors and low cost, low power markets. In other words point their broadside cannons at Broadcom.

 

[NinoPino]

Intel will show somenthing with risc V...
The x86 server market will be mixed with P cores E cores and risc cores. maybe some Gpu multi purpose in the future...

If you mean a CPU with mixed x86-RiscV, I doubt. A CPU like this should divide total number of cores between x86 and RiscV so it would be weak on both sides.

 

[NinoPino]

I don't know what Intel has planned with Risc V but my assumption was they'd start with infrastructure products like data center switches and routers, set-top/CMTS, cable modems, and PON/DSL, Ethernet NICs, filters and amplifiers, wireless connectivity solutions, embedded processors and low cost, low power markets. In other words point their broadside cannons at Broadcom.

Intel just leaved networking, storage and other markets to concentrate funds on CPUs and foundry.
Thinking of businesses that could immediately use RiscV without hurting x86 business, my mind go to phone SOCs and GPUs for datacenters, in the style of H100/MI300.

 

[bit_user]

RISC-V is an open standard (previously open source) CPU architecture

LOL, what??? Do you even understand what you're saying?

No, just "open standard". Period.

 

[Amdlova]

If you mean a CPU with mixed x86-RiscV, I doubt. A CPU like this should divide total number of cores between x86 and RiscV so it would be weak on both sides.

With this glued tech, you can mix all cores and mix some strength and weakness... new set of instructions for mixed use... only matters it's die size

 

[bit_user]

With this glued tech, you can mix all cores and mix some strength and weakness... new set of instructions for mixed use... only matters it's die size

Yes, but no - it won't happen. It's too complex for the OS to span multiple ISAs for the value it provides, especially when emulation works pretty well for most purposes. I don't see it happening.

What we could see is some SoCs having a mix of wider, slower cores and faster, narrow cores:

​

Imagination and Ventana to Build a RISC-V CPU-GPU Platform

New RISC-V platform could address client applications.

www.tomshardware.com

​

The wider, slow ones could run GPU and AI code. Maybe also some other threads, in a pinch.

 

[Findecanor]

What we could see is some SoCs having a mix of wider, slower cores and faster, narrow cores:
[...]
The wider, slow ones could run GPU and AI code. Maybe also some other threads, in a pinch.

That already exists, sort of.

The Sophgo SG2380 has 16 × SiFive P670 cores (4-issue OoO, 128-bit Vector), and 8 × SiFive X280 cores (2-issue in-order, 512-bit Vector registers) with a TPU.
However, it does not look as if there is a cache-coherency lines between the two core clusters which would allow them to run processes as if the same system.