Question Weird names on mu Ram timings

Feb 15, 2019
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:confused_old:Hey, i cant remeber what ram i have but i am able to run it at 3066mhz. Now the timings wAs set to auto and i know they can be alot better. Plus the timing names are super weird. I just want help to know which the trcd, trp, and tras. Idk how to post a picture but the names in my bios are ... trcdrd, trcdwr, dram ras# pre time, dram ras# act time. And then alot more but i guess these are the right ones? But i dont know which is which. Thanks for helping
 

Darkbreeze

Titan
Moderator
CAS Latency (tCL/tCAS):


Wikipedia: “The number of cycles between sending a column address to the memory and the beginning of the data in response. This is the number of cycles it takes to read the first bit of memory from a DRAM with the correct row already open. Unlike the other numbers, this is not a maximum, but an exact number that must be agreed on between the memory controller and the memory.”


CAS Latency is the most widely talked about and compared memory timing. The CL timing is an exact number, the base time that it takes to get a response from memory in the best possible scenario described above, referred to as a “page hit.” The other primary timings (other than command rate) are minimums. It’s important to remember that although we’ll be talking about how these timings relate to reading data from memory, that’s just one thing they affect.


RAS to CAS Delay (tRCD):


Wikipedia: “The minimum number of clock cycles required between opening a row of memory and accessing columns within it. The time to read the first bit of memory from a DRAM without an active row is tRCD + CL.”


RAS to CAS is one potential delay to read/writes. tRCD is the number of clock cycles it takes to open a row and access a column. If a request for data is made when there are no rows open, referred to as “page miss,” it will take at least tRCD + CL clock cycles for the CPU to receive the first bit of data in response.


Row Precharge Time (tRP):


Wikipedia: “The minimum number of clock cycles required between issuing the precharge command and opening the next row. The time to read the first bit of memory from a DRAM with the wrong row open is tRP + tRCD + CL.”


If the wrong row is open (“page miss”), it needs to be closed (precharged), then the next needs to be opened, then the column within the row needs to be accessed. This therefore takes tRP + tRCD + CL time.


Row Active Time (tRAS):


Wikipedia: “The minimum number of clock cycles required between a row active command and issuing the precharge command. This is the time needed to internally refresh the row, and overlaps with tRCD. In SDRAM modules, it is simply tRCD + CL. Otherwise, approximately equal to tRCD + 2×CL.”


Also known as Activate to Precharge Delay or Minimum RAS Active Time. The first equation (for SDRAM) is the relevant one here, but it should be more than that. We’ve seen multiple different “true” ways to calculate tRAS, but given the complexity of memory operations, good old trial and error remains the easiest. For example, we somehow booted with memory at 16-16-16-26, and that doesn’t make sense by anyone’s rules.


Command Rate (CR/CMD/CPC/tCPD):


AMD: The amount of time, in cycles, between when a DRAM chip is selected and a command is executed. 2T CR can be very beneficial for stability with high memory clocks, or for 4-DIMM configurations.


Also known as Command Period. This will either be 1T or 2T on modern memory, with 1T being faster. Despite the unique -T notation, this is measured in clock cycles like the other timings. There’s generally a very small performance delta between the two options.
 

Darkbreeze

Titan
Moderator
As presented in your ADVERTISED memory specifications, those timings will be located, in order, as follows: CL-tRCD-tRP-tRAS-CMD

So when a set of sticks says it has 16-18-18-36 then it has CL16, tRCD 18, tRP 18 and tRAS 36. Command rate is generally 1T or 2T but isn't usually listed in the main advertised specifications although you can almost always find it on the memory module's product page.
 

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