What are the pros and cons to faster speed DDR4-2666 to a higher cas but ddr4-3200? both 32gb

Tax6132

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I'm a bit confused on this, I hear the analogy all the time about a highway being wider etc but what does that mean? does it mean I'll be able to have more tabs open without "lag" opening or refreshing more. I could be completely wrong but I don't understand this.

Thanks for reading.
 
Solution
Dividing CAS by MHz determines latency, which is one piece of the puzzle. This is because as clock speed increases, each clock cycle takes less time. So 2400MHz CL12 would have the same actual CAS latency as 3000MHz CL15, 10ns. Even though they are the same latency, the 3000 would have 25% more bandwidth and would be much faster. Imagine you are getting 10 books off a bookshelf at the library. The latency is how long it takes you to locate the individual books, and the bandwidth is how fast you're actually able to carry the books from the shelf to the check-out desk. Both matter, but bandwidth usually matters more.

scuzzycard

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MHz is more important than timing. To give you a basic idea, 2800 at CL13 would beat 2666 at CL12, but 2666 at CL12 would beat 2800 at CL15. The 3200 would almost certainly toast the 2666.

It's mostly academic, though. You won't notice the difference in gaming or web surfing, for sure, but a synthetic test will show a few percent difference.
 

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What does dividing the CAS with the MHZ do? I herd someone tell me to do that to decide which is the best ram to purchase.
Also is it better to have heavy hitting ram with a higher mhz or lower mhz but lower cas
 

scuzzycard

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Dividing CAS by MHz determines latency, which is one piece of the puzzle. This is because as clock speed increases, each clock cycle takes less time. So 2400MHz CL12 would have the same actual CAS latency as 3000MHz CL15, 10ns. Even though they are the same latency, the 3000 would have 25% more bandwidth and would be much faster. Imagine you are getting 10 books off a bookshelf at the library. The latency is how long it takes you to locate the individual books, and the bandwidth is how fast you're actually able to carry the books from the shelf to the check-out desk. Both matter, but bandwidth usually matters more.
 
Solution


Close, but not quite.

Tcas or Tcl is the number of cycles (not transfers) that will elapse between the memory module registering a read command and the data from the first word of that read burst being strobed onto the IO bus.

Commands must be carefully timed so that they do not interfere with eachother. DDR3 and DDR4 have burst lengths of 8 words, so each read command actually reads 8 words at once and every write command actually writes 8 words at once. When read, these words are serialized onto the IO bus and trasferred over 4 cycles (two transfers per cycle, hence DDR) and when written, these words are deserialized from the IO bus over 4 cycles. Accordingly, it is possible to issue a chain of read commands with one command every Tccl (Column Command Latency) cycles, or the same with write commands; it is not possible to tightly interleave read and write commands. Tccl is 4 cycles for DDR3 and works slightly differently in DDR4.

When properly chained, the IO bus can be kept busy nearly 100% of the time.