What exactly happens in a clock cycle?

[Deus Gladiorum]

Hey guys, so pretty recently I've been doing a lot more research on CPU architecture and for a while I've known that clock rate is not synonymous with instruction rate. So my question is, what exactly happens in a clock cycle? Is it the time it takes for a transistors to switch from 0 to 1 and vise versa? Or is it something else? Any help on the subject would be great!

Also, as a bit of a side question, is it possible to complete more than one instruction in a single cycle? If so, could someone explain how in relatively simplified terms (I understand things like Instruction Pipelines and such to some extent).

 

[hunter315]

The clock signal is just a little square wave going on that everything gets synchronized off of. The clock doesn't apply to the standard logic gates, it only really applies to the memory elements at each end of a pipeline stage. When the clock signal rises it opens up the memory cell and lets charge flow in or out of it(write/read), then it closes off again to preserve the state while the gates on the other end are in indeterminate states. Its basically just the conductor of the orchestra, its just for synchronization.

Easiest way to present this example is assume you have a pipelined ALU and FPU and it takes you 3 cycles to do an integer multiplication and 8 to do a floating point multiplication. Consider this code sample
for (j=0; j < 100; j++)
{
a[j]=a[j]*2;
b[j]=b[j]*2.5;
}
Most processors can grab multiple instructions at a time and start them going, this would start loading the a[j]*2 into the ALU as fast as it could and the b[j]*2.5 into the FPU, so after 3 cycles you would get your first a[j] out, and after 8 you would start getting an a[j] and a b[j] out each clock cycle, so while your latency on every instruction is >1 clock cycle your average throughput is ~2 instructions/clock cycle