They would be without the buffed buffers and caches. It just turns out that increasing on-chip SRAM, which is itself ludicrously expensive, to get by on GDDR6(X) is still cheaper overall than HBM and good enough in the consumer space at least for now.Most games aren't limited by memory bandwidth, so it didn't make financial sense to use HBM over GDDR6x.
They would be without the buffed buffers and caches. It just turns out that increasing on-chip SRAM, which is itself ludicrously expensive, to get by on GDDR6(X) is still cheaper overall than HBM and good enough in the consumer space at least for now.Most games aren't limited by memory bandwidth, so it didn't make financial sense to use HBM over GDDR6x.
That said, the main reason HBM costs more is low volume. If there was mass adoption of HBM2/3, it would become marginally more expensive than GDDR6.
Dies are usually tested while they are still on the wafer to avoid wasting time cutting and handling defects, so there shouldn't be many defects making it into HBM stacks and the stacks themselves get tested again before shipping to the customer.Once you bind an IC onto the package substrate, it's probably really hard to correct it. And HBM based systems have more points of failure per substrate over a single die on a substrate, and all of these points have to pass for it to work.
The defects may not be there when they arrive for final assembly, but something may happen during the final assembly.Dies are usually tested while they are still on the wafer to avoid wasting time cutting and handling defects, so there shouldn't be many defects making it into HBM stacks and the stacks themselves get tested again before shipping to the customer.
While do bring up a point about MCM manufacturing being sufficient for Zen 2/3, I don't think there's "thousands of signals". Most of the diagrams I've seen say IF is a 32-bit wide bus in each direction, so 128 lines total (64 for data, 64 for ground) per CPU die. So at most this is 1024 lines (half of which are ground) for an 8-die EPYC. The other thing is the package itself from what I can tell is no more different than a bog standard PCB. The interposer for HBM based devices is typically silicon based.On the points of failure side of thing, I think AMD's Zen 2/3 Ryzen/TR/EPYC lineups have proven that having thousands of signals between CCD and IOD is not a major yield or reliability issue and Intel's crazy 47 tiles monster shows that Intel is fairly confident in its fancy packaging abilities.
Not much information out there besides the 32B/fclk read and 16B/fclk write on marketing slides. Something is clearly not symmetrical there.Most of the diagrams I've seen say IF is a 32-bit wide bus in each direction