What Is RING RATIO?

[FORMULADRIFT3R]

Hello everyone I need some help figuring out what Ring Ratio is

Thank You

 

[WyomingKnott]

Perhaps you can give us some context? Where does this show up? The only thing that I find by googling the term is the ratio of the lengths of your second and fourth fingers.

EDIT: On further consideration, check this out: http://www.overclock.net/t/1411077/haswell-overclocking-guide-with-statistics

 

[Dark Lord of Tech]

http://linustechtips.com/main/topic/41234-intel-haswell-4670k-4770k-overclocking-guide/
Look under < CPU Ring Bus Stability

 

[Pinhedd]

Hello everyone I need some help figuring out what Ring Ratio is

Thank You

The ring bus is the interconnect topology that connects the cores, system agent, IGP, and memory controller together. It's called a ring bus because the bus topology looks like a ring.

The SandyBridge and IvyBridge microarchitectures use three clock domains inside of the CPU package. One is for the IGP (if present), one is for the PCIe reference clock, and the other is for all other components including the CPU cores, caches, ring bus, and system agent / memory controller.

What this means is that the CPU cores, caches (specifically the shared L3 cache), system agent (QPI, DMI, PCIe roots), and memory controller are all driven by the same clock. While this is conceptually simple, this presents a small problem with respect to power efficiency. While each core can be placed into a number of low speed states to save power, the system agent and L3 cache can only be placed into a low power state if the entire CPU is placed into a low power state.
There are some use cases in which it may be desirable to have the IGP running full tilt (such as hardware decoding video) with the rest of the CPU package running in a low power state. Under the Sandybridge/Ivybridge design, if the IGP needs fast access to the L3 cache while the CPU is in a global low power state it has to bring the CPU into a higher power state even though the CPU isn't being tasked with anything in particular.

Haswell works around this by decoupling the CPU cores from the rest of the non-IGP hardware. This results in a slight increase in L3 cache latency due to the L3 cache requests having to cross clock domains (which is not a big deal) but allows the CPU cores to remain in a low power state while the SA/L3 Cache enter the high power state to feed the IGP.

On Sandybridge/Ivybridge the ring bus ratio is fixed at 1:1. On Haswell, it can float.