Info What We Know About DDR5 So Far

DDR5-3200 RAM will see an increase of 1.36x in bandwidth compared to DDR4-3200. However, DRAM chips are expected to ship with a bandwidth of 4800MT/s, or 1.87x that of DDR4-3200 RAM.
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The DDR5 RAM chips are expected to start at 4800MT/s, which would be a 1.87x increase in bandwidth compared to DDR4-3200 RAM. The DDR5 standard has an official limit of 6400MT/s, but we may see some memory companies push that further.
All other information I've seen indicates that the only source of increased bandwidth for DDR5 is from increased transfer rate, such that if DDR5 and DDR4 were running at same speed they'd have the same bandwidth. As has been the case going back all the way to the original DDR SDRAM. Is there just lots of typos/bad math in this article, or is there some other factor increasing the bandwidth of DDR5 compared to DDR4 other than transfer rate?
 

XaveT

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<nit-picky>
The article has some repeated text, can we get a bit of a clean-up? I only mention it because it was distracting trying to read through it.
</nit-picky>
 

Xajel

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All other information I've seen indicates that the only source of increased bandwidth for DDR5 is from increased transfer rate, such that if DDR5 and DDR4 were running at same speed they'd have the same bandwidth. As has been the case going back all the way to the original DDR SDRAM. Is there just lots of typos/bad math in this article, or is there some other factor increasing the bandwidth of DDR5 compared to DDR4 other than transfer rate?
DDR5 is rumoured to have 16n prefetch mode, which if it happens means at the same clock DDR5 should be twice as fast as DDR4.

It's the same as what DDR3 brought compared to DDR2 which also doubled it compared to DDR.

DDR3 and DDR4 both had 8n prefetch, DDR5 is still unconfirmed, some says it has 8n like DDR3 & 4. While some says it has 16n, like GDDR5 & HBM2.
 

jimmysmitty

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A 32GB stick of DDR5 RAM should have the same density as a 16GB DDR4 stick while delivering roughly twice the performance.
This line doesn't make any sense. If a it is a 32GB stick, although a different pin layout most likely, it is twice a s dense as a 16GB DDR4 stick.

Now if you are talking about the number of DRAM modules on the stick then I could see it being true if its has 16 per stick (8 per side).
 

PaulAlcorn

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All other information I've seen indicates that the only source of increased bandwidth for DDR5 is from increased transfer rate, such that if DDR5 and DDR4 were running at same speed they'd have the same bandwidth. As has been the case going back all the way to the original DDR SDRAM. Is there just lots of typos/bad math in this article, or is there some other factor increasing the bandwidth of DDR5 compared to DDR4 other than transfer rate?
Here's a bit more info on the matter View: https://twitter.com/david_schor/status/1116168728046002176
 
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DDR5 is rumoured to have 16n prefetch mode, which if it happens means at the same clock DDR5 should be twice as fast as DDR4.

It's the same as what DDR3 brought compared to DDR2 which also doubled it compared to DDR.

DDR3 and DDR4 both had 8n prefetch, DDR5 is still unconfirmed, some says it has 8n like DDR3 & 4. While some says it has 16n, like GDDR5 & HBM2.
This doesn't really make sense either. If doubling prefetch doubled bandwidth for the same transfer rate, why does DDR2 have the same bandwidth as DDR if they're both running at the same speed? Same for DDR3 vs DDR2. Same for GDDR5X vs GDDR5. Also, even if increasing prefetch did increase bandwidth at the same transfer rate, according to the article DDR5 only has 36% more bandwidth than DDR4 at the same transfer rate, not 100%:
DDR5-3200 RAM will see an increase of 1.36x in bandwidth compared to DDR4-3200.
Edit: I should clarify that when I say bandwidth I'm talking about theoretical max bandwidth.
 
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vaughn2k

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In March 2017, JEDEC, the group developing the DDR standard as well as other memory and storage standards, announced that it would release the DDR5 specification in 2018

This is from the JEDEC Specification JESD21-C Configurations for Solid State Memories maintained by JC41 JEDEC Committee - which is also the committee developing the DDR standard.
JEDEC Organization, as a whole, is not only responsible for memory standard, but all semiconductor, and microelectronics standardization for interoperability.
 

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