Question Why doesn't the 7800x3D have 128MB of 3D V-cache?

[80251]

From what I understand the 3D V-cache only attaches to one CCD, but even if the 7800x3D only has one CCD why can't it get the same amount of 3D V-cache as the 7900x3D and the 7950x3D? Was this a marketing decision (i.e. for product line differentiation) or an engineering decision?

 

[Roland Of Gilead]

Was this a marketing decision (i.e. for product line differentiation) or an engineering decision?

Hey there,

Short answer, yes. Exactly. Performance/price segmentation. The more expensive parts have higher L3 cache. But, the 7800x3d often outperforms the higher end parts at pure gaming.

 

[tennis2]

Fun fact, even for non-3DVcache CPUs, [for gaming] cache size explains the majority of performance difference between CPUs when frequency is normalized. Core count still largely exceeds what actually gets used by games.

Higher core count CPUs typically have lower frequencies than 6c or 8c CPUs due to power/heat limitations, which is why those 6c or 8c CPUs generally dominate the perf/$. They're not "wasting" unused cores in gaming, and they're getting the frequency benefit.

So yes, as Roland said, if they gave the 7800X3D more 3DVcache, they'd cannibalize sales of the 7900/50 X3D skus almost entirely.

 

[Eximo]

From what I understand the 3D V-cache only attaches to one CCD, but even if the 7800x3D only has one CCD why can't it get the same amount of 3D V-cache as the 7900x3D and the 7950x3D? Was this a marketing decision (i.e. for product line differentiation) or an engineering decision?

Well, since they are using a modular design it is pretty straightforward.

Base CCD has 32MB of cache.
3D VCache adds 64MB
32+64 = 96MB

7950X 3D and 7900X3D have a single CCD with the additional cache, but still get the cache that each CCD has on it.
32+32+64 = 128MB

A dual X3D chip if made would have 196MB of cache.

Not sure they can stack multiple 3D Vcache chips, but if they could it would end up being 160MB rather than 128MB.

 

[80251]

So the largest 3D V-cache is 64MB? Will the 9000x3D series be bringing more 3D V-cache to each product tier?

 

[Eximo]

I think the only size is 64MB. I don't believe so, still looks to be 96MB for the 9800X3D.

I understand they may have flipped things around so the cache is underneath the CCDs which may be what allows for the higher clock speeds, but we'll have to wait for people to get it in hand I think.

 

[kognak]

Well, since they are using a modular design it is pretty straightforward.

Base CCD has 32MB of cache.
3D VCache adds 64MB
32+64 = 96MB

7950X 3D and 7900X3D have a single CCD with the additional cache, but still get the cache that each CCD has on it.
32+32+64 = 128MB

A dual X3D chip if made would have 196MB of cache.

Not sure they can stack multiple 3D Vcache chips, but if they could it would end up being 160MB rather than 128MB.

Can't stack because it would add another layer on already struggling heat transfer path from cores to IHS. It would reduce clocks even further down, less than 4.5GHz. Can't make cache die bigger either, it needs to align with cache on core die due connections between cache segments. It's pretty much maxed, AMD is cramming twice as much cache on cache die taking about same area as 32MB on core die.
Also 4+4 dual CCD doesn't make any sense, a single thread would see exactly same amount cache as on single CCD 8-core. No performance benefit and all the dual CCD downsides. And uses two CCDs which could be used in higher skus or two single CCD skus.
However, Zen5 very likely can stack cache dies. AMD moved cache die under core die, connections to substrate go through cache die which is relatively trivial to stack(manufacturing might have extra challenges). This arrangement eliminates thermal issues as core die is always next to IHS. Having vcache doesn't reduce clocks anymore apart from binning differences. If datacenter or workstation space has demand for even bigger cache per CCD skus, those CCDs will trickle down to desktop space too. AMD is not going to create one just for gamers.