Actually, if Intel were to implement an ondie memory controller the increase would be a lot smaller than AMD's increase was. This is because with Intel's long pipeline they were forced to write excellent prefetch algorithms because frequent misses requiring a rerun through that pipeline after obtaining the correct memory would have cost a large loss of performance.As everyone knows the P4 loves cache and lots of memory. So the increase would be alot bigger.
Your logic doesn't make sense. Both the on-die memory controller and aggressive pre-fetching are ways of reducing overall fetch latency. The on-die memory controller makes it so memory fetches take less time while prefetching allows more cache hits. Both have the same end result: less latency for load/stores.Actually, if Intel were to implement an ondie memory controller the increase would be a lot smaller than AMD's increase was. This is because with Intel's long pipeline they were forced to write excellent prefetch algorithms because frequent misses requiring a rerun through that pipeline after obtaining the correct memory would have cost a large loss of performance.
AMD on the other hand kept their pipeline small, and so they had the luxury of being able to live with mediocre prefetching. If they have to recycle through their pipeline after collecting new memory it's not nearly the performance loss that it is for Intel.
Depends. If it weren't for the power wall Netburst is hitting, I would say that the on-board memory controller would help greatly for future (4+ GHz) processors as the barrier between processor and memory would grow even larger. DDR2 doesn't help much considering its latency timings are even greater.Thus when AMD implemented the ondie controller to reduce latency to a theoretical minimum this benefitted them greatly beause with the lower latency their frequent prefetch misses cost them that much less of a performance loss. But with Intel, who has good prefetch logic, there are many less prefetch misses and so would have much less to gain from a lower memory latency.
Again, depends on the scaling. At 3 GHz, I'd agree with you, at 4 GHz, it'd be an entirely different story.This is also why AMD systems gain much more from fast RAM timings than Intel systems do, because that too is just a trimming of the memory latencies.
This is not to say that Intel wouldn't gain at all from an ondie controller. They would just gain noticably less than AMD did.
Also, it is ironic that Intel would push PCIe, a highly point-to-point, sophisticated interconnect, while keeping their usual CPU FSBs shared. AMD is actually doing the opposite: it's not doing PCIe as vigorously, but they're implementing more advanced CPU interconnects...This link width negotiation allows for some flexibility in designing systems and integrating devices with different lane widths, but it will make for some headache in the consumer space. People will have to figure out how to match link widths with device widths, and they'll be initially confused by situations in which the link is one width and the connector another, as is the case with an NVIDIA card plugged into an x16 slot attached to an x8 link.
The NVIDIA card plugged into the x8 link will talk to the switch and figure out that the link is only x8. It will then train down accordingly and transmit data at the appropriate x8 rate.
True, Intel is intel, but I think they might have learned something... Hopefully.intel well should do it. but intel being intel they won't they will carry on increasing the FSB, cache and clock.
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