Question Why has PC (System Memory/RAM) "First Time Boot Initialization" been largely the same?

[Kamen Rider Blade]

It feels like the BIOS/UEFI software vendors haven't really updated the "First Time RAM Initialization" routine to use all the available hardware on the PC.

We're coming upon the age of 24 GB / 48 GB DIMM sticks being common with DDR5.

Consumer RAM/System Memory capacities are only going to get larger with time.

Not to mention (Enterprise/Server) level "RAM/System Memory" capacities are getting ever larger with longer "First Boot Cycles".

NOTE: " I could be very wrong on this aspect ", that the BIOS/UEFI only counts/initializes RAM in a Single-Threaded mode and doesn't use all available Cores on a Multi-Core CPU setup.

Does anybody know IF the Initial "First Boot RAM Initialization" utilizes all available cores on the CPU to count the total available memory in parallel for a faster initial Boot sequence?

 

[kerberos_20]

hmm well...at first boot initialisation...when firmware has not yet stored your ram initialisation data, it goes somewhat as folows:
base enviroment initialisation
initialise CPU cache as a RAM (as the CPU has to work somewhere and uefi ROM is slowpoke for that)
initialise SMBUS on PCH through PCI enumeration
reads SPD EEPROM from each dimm
configure memory controller(s) with SPD data
configure PCH memory mapping

now during memory controller configuration...it usualy fails at first try because SPD has only few RAM settings stored, and some firmwares can also ignore some SPD bits....anyway RAM to work needs way more settings than SPD offers, so firmware has to guess it, (it should have some lookup table) so this part takes a bit and few reboots until it succeeds, once firmware knows your RAM, it saves it, so any next boot is much faster until you decide to clear it with cmos reset


and to answer your question...to use multiple cores
if theres some parallel work to do, while one core busy with one task, do another task insted on second core
but in this case it has to be serial, sure if you have multiple socket mainboard with multiple memory controllers, this could be run in parallel...but no clue how its done on server boards if its initialising each socket and each memory controller in serial or parallel either way it would still wait for slowest to initialise memory controller in there

 

[Kamen Rider Blade]

hmm well...at first boot initialisation...when firmware has not yet stored your ram initialisation data, it goes somewhat as folows:
base enviroment initialisation
initialise CPU cache as a RAM (as the CPU has to work somewhere and uefi ROM is slowpoke for that)
initialise SMBUS on PCH through PCI enumeration
reads SPD EEPROM from each dimm
configure memory controller(s) with SPD data
configure PCH memory mapping

now during memory controller configuration...it usualy fails at first try because SPD has only few RAM settings stored, and some firmwares can also ignore some SPD bits....anyway RAM to work needs way more settings than SPD offers, so firmware has to guess it, (it should have some lookup table) so this part takes a bit and few reboots until it succeeds, once firmware knows your RAM, it saves it, so any next boot is much faster until you decide to clear it with cmos reset


and to answer your question...to use multiple cores
if theres some parallel work to do, while one core busy with one task, do another task insted on second core
but in this case it has to be serial, sure if you have multiple socket mainboard with multiple memory controllers, this could be run in parallel...but no clue how its done on server boards if its initialising each socket and each memory controller in serial or parallel either way it would still wait for slowest to initialise memory controller in there

Is there a limit as to how fast the CPU can initialize the initial RAM count?

Is the memory controller the limit due to one set of RAM being accessed at any given time in each Memory Channel?

Or is there a different fundamental limit I'm not thinking about?

 

[kerberos_20]

Is there a limit as to how fast the CPU can initialize the initial RAM count?

Is the memory controller the limit due to one set of RAM being accessed at any given time in each Memory Channel?

Or is there a different fundamental limit I'm not thinking about?

The speed at which a CPU can initialize the initial RAM count is limited by the memory controller, which controls the communication between the CPU and the RAM. The memory controller can only access one set of RAM at a time in each memory channel, which can limit the overall speed of the initialization process. Additionally, the speed of the RAM itself can also be a limiting factor. Other factors such as the bus speed and the number of memory channels can also affect the initialization speed.

 

[Kamen Rider Blade]

The speed at which a CPU can initialize the initial RAM count is limited by the memory controller, which controls the communication between the CPU and the RAM. The memory controller can only access one set of RAM at a time in each memory channel, which can limit the overall speed of the initialization process. Additionally, the speed of the RAM itself can also be a limiting factor. Other factors such as the bus speed and the number of memory channels can also affect the initialization speed.

So it's not the lack of CPU Cores or Frequency that is the main hindrance currently.

In summary, the current major bottle necks are:

• The # of Primary Memory Channels that a Memory Controller has access to, AKA how many DIMM slots within your Memory Channels are filled out.
• In the case of DDR5 & future DDR# versions > 5, how many "Sub Channels" within each DIMM Primary Memory Channel that you have access to.
• How fast is the RAM operating at, bus speeds, latency settings, etc.

Those are the bigger bottle necks at the moment that would affect initialization, right?