Well, we are getting pretty close to the point of diminishing returns on 2D silicon. MCM and stacking are going to be the next big things, but that shouldn't be this generation for Nvidia and AMD.
Probably why they are planning for PCIe 5.0 and its 600W connector. They are aware that there is only so much they can do over the next few years until there is a drastic improvement in efficiency. TSMC is only going to take them so far Also note that the ones they advertise as the new nodes are targeted at low power devices, GPUs require a different approach, so while they still call it N6, there is usually a difference in logic size between the stuff that runs a SoC and the stuff that runs at high clock speeds)
I know Intel is trying to be optimistic, but we saw how that went for them with 10nm. Not going to be long before TSMC tries to make an attempt. Seems like they are looking at N2 for going GAA. Intel looks to be heading to Ribbon FET for their 20A node.
Keep in mind they are both switching to EUV hard which could go very well or very bad.
But with each rough generation boasting about 15-25% improvement, chips of the same class/size should be expected to be that much faster/denser.