[citation][nom]Crashman[/nom]OK, let me explain this to you: The chipset has 36 PCIe 2.0 lanes, not 32. Each of those controllers uses EXACTLY one PCIe 2.0 lane, and there are two PCIe 2.0 controllers. That means you need EXACTLY two PCIe 2.0 lanes, of which you have four. It's impossible to shove more data into those controllers, because the interface on those controllers is 5.0 Gb/s.Now do you see why they couldn't add on?[/citation]
Yes I get that part, but maybe I misunderstood the whole point?
Isn't the issue, that not all the onboard junk can be operational at the same time, because of controllers sharing the pathways? Isn't that what asrock claims it has solved? Or is it simply the slowdown measured, that they've claimed to have solved?