You Intel Followers are the most Stupid People

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girish

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how could be the clock speed ramped up by using deeper pipelines? as intel presentation (get it at ) on P4 architechture says, deeper pipelines means smaller shorter stages (checkpoints as some say) and that allows faster clocks. i dont agree.

instruction pipes ahould work at whatever MHz the processor works. even with just a faster clock, its going to work faster. and increasing the clock further with make it even faster. then, what has the smaller circuits to do with it?

girish

<font color=blue>die-hard fans don't have heat-sinks!</font color=blue>
 

Raystonn

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"instruction pipes ahould work at whatever MHz the processor works. even with just a faster clock, its going to work faster. and increasing the clock further with make it even faster. then, what has the smaller circuits to do with it?"

Well with that logic why don't we all just use 1st gear in our vehicles on the freeway at 65-70mph? We'd have better acceleration. In reality, however, 1st gear cannot reach such speeds. The high RPMs would tear the engine to pieces. It wasn't physically designed to cope with the heat, tension, extreme torque and heavy vibrations that would be produced. It would just blow out.

CPUs are no different. You can't simply up the clockspeed infinitely. Even if you can cool it sufficiently it still will not work. There are other physical considerations that must also be taken into account. These include, but are not limited to, the capabilities of individual components (transistors, etc) to respond as quickly as desired. Different electrical components are used at different speeds at different stages of a pipeline. On older pipeline designs, such as on the Pentium III, most electrical components might not be hitting this hard physical limitation for component latency on most areas of the pipeline. However, there's always that small part of one or two stages of a pipeline where a few components are maxxed out and you cannot increase the speed of the whole pipeline (increase the CPU clockspeed) without frying these components taht are only used in 1 or 2 stages. This is when a pipeline redesign is desired. You usually spread out these component accesses along a couple extra pipeline stages so they are no longer a bottleneck to further clockspeed increases. This lets you up the clockspeed on the whole CPU without hitting any component bottlenecks on 1 or 2 areas. Rather you can allow yourself to ramp up clockspeed to the physical limitation of nearly all components and stages at once, fully utilitizing the design, and reaching the highest levels of performance as yet achieved.

-Raystonn

= The views stated herein are my personal views, and not necessarily the views of my employer. =
 

funkdog

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The IPC for a P4 is still 1. 1 instruction per clock cycle. The reason it has to have a 1.7mhz clock is to compensate for the length the instruction has to travel. Here I thought you worked for intel. 1.7 x 1 = 1.7 as per your equation. IPC = instructions per clock cycle
 

Raystonn

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Actually, the average number of instructions you can perform per clock cycle varies according to what instructions you are executing. Branch mispredictions also incur penalties, further lowering the average figure. There may be an instruction that completes in 1 clock cycle, but they certainly all do not.

-Raystonn

= The views stated herein are my personal views, and not necessarily the views of my employer. =