News Intel Shows New Stacked CFET Transistor Design At ITF World

[Admin]

Intel’s Ann Kelleher showed a render of the new Complementary FET (CFET) transistor during her presentation at imec’s ITF World conference.

Intel Shows New Stacked CFET Transistor Design At ITF World : Read more

 

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Once you have GAA where the transistor channel isn't tied to the substrate anymore, the only limit to how many transistors you can stack on each other is thermal density. CFET is only the logical first step beyond GAA.

 

[PaulAlcorn]

Once you have GAA where the transistor channel isn't tied to the substrate anymore, the only limit to how many transistors you can stack on each other is thermal density. CFET is only the logical first step beyond GAA.

Most of the industry predicts that forksheets come first, actually.

 

[InvalidError]

Most of the industry predicts that forksheets come first, actually.

Forksheets are nothing more than two GAA stacks sharing a gate drive signal for space efficiency. IMO, this is far too obvious an improvement to call out separately as it makes no sense to build a GAA inverter gate/buffer any other way.

 

[PaulAlcorn]

Forksheets are nothing more than two GAA stacks sharing a gate drive signal for space efficiency. IMO, this is far too obvious an improvement to call out separately as it makes no sense to build a GAA inverter gate/buffer any other way.

They're called out in roadmaps separately, as they increase density significantly and will serve for a few years before CFET comes to fore. Bringing nFET and pFET together seems to be a pretty significant and complicated advance to me, as well as the use of the dielectric barrier.

 

[InvalidError]

Bringing nFET and pFET together seems to be a pretty significant and complicated advance to me, as well as the use of the dielectric barrier.

The only difficulty in "bringing them together" was that with FinFET, manufacturers were still stuck in 2D for transistor construction. With GAA eliminating this restriction, almost any transistor configuration is possible now. It doesn't need to stop at stacking only one p-n pair, you could build many 2-3 inputs logic functions vertically depending on how many active layers you are willing to stack.

The only thing that makes forked "easier" is that it requires half as many total layers vs stacked CMOS pairs but it also has only about half as much areal density.

As I have written before, the main problem is power density: if you stack transistors N-high, you need to find a way to deal with having up to N-times that much power density.

We know from NAND that layers are at least 20X cheaper than die area. Now that the vertical genie for high-speed CMOS is out of the bottle, stacked transistors are inevitable.

 

[Arbie]

I used to believe what Intel said; and excited to watch it come true. Those were the days.

 

[MattTraversoPhD]

The only difficulty in "bringing them together" was that with FinFET, manufacturers were still stuck in 2D for transistor construction. With GAA eliminating this restriction, almost any transistor configuration is possible now. It doesn't need to stop at stacking only one p-n pair, you could build many 2-3 inputs logic functions vertically depending on how many active layers you are willing to stack.

The only thing that makes forked "easier" is that it requires half as many total layers vs stacked CMOS pairs but it also has only about half as much areal density.

As I have written before, the main problem is power density: if you stack transistors N-high, you need to find a way to deal with having up to N-times that much power density.

We know from NAND that layers are at least 20X cheaper than die area. Now that the vertical genie for high-speed CMOS is out of the bottle, stacked transistors are inevitable.

There are other major limitations to stacking more than 2 layers in CFET, specifically routing. Each transistor needs 3 contacts (source, drain, gate) and sometimes transistors can share multiple. CFET works because most transistors in CMOS architecture are paired so they can share contacts (usually the source and the gate). If you start adding 3 or 4 transistors in a stack, you quickly run out of surface area for all the contacts to connect to all the transistors in a stack. When transistors in a stack aren't paired, it also becomes challenging (but surmountable) to vertically isolate their gates from each other.

3DNAND is a special case because little routing is needed. Each stack shares 1 source and 1 drain and the gates are shared by thousands of transistors in a plane, each. Even still, the staircase structures needed to contact each NAND gate are complex and non-trivial to manufacture.

Mono CFET also presents challenges to create the nanosheets and then etch deep enough that will probably limit the number of ribbons in a stack for a while. Sequential CFET with several layers of interconnects between the ribbons would be a possibility for solving both the routing problems and the stack pattern problems, but at that point, you're looking at something more in common with Foveros/active interposer than a monolithic chip solution.

Bottom line, although possible, I don't see it very likely to move beyond a stack of 2 paired transistors of CFET quickly.

I agree with your assessment of Forksheet. It's basically GAAFET with a dielectric to split each fin in half so that both PMOS and NMOS operate on the same fin.

I'm a former technical trainer in semiconductor manufacturing. I trained new hires on process flow and capabilities. I've been writing articles on medium about finfet, gaafet and cfet for a more general audience. I won't link them, here, but you can look me up.

 

[InvalidError]

There are other major limitations to stacking more than 2 layers in CFET, specifically routing. Each transistor needs 3 contacts (source, drain, gate) and sometimes transistors can share multiple. CFET works because most transistors in CMOS architecture are paired so they can share contacts (usually the source and the gate). If you start adding 3 or 4 transistors in a stack, you quickly run out of surface area for all the contacts to connect to all the transistors in a stack. When transistors in a stack aren't paired, it also becomes challenging (but surmountable) to vertically isolate their gates from each other.

I don't see how vertical gate isolation would be any more difficult than the N-channel and P-channel ribbon isolation when gates have always been vertically isolated from everything else in planar FETs - just don't etch a hole in the silicon oxide layer between layers that aren't supposed to connect to each other.

As for sharing contacts, one stage's output is the next stages' input. Full adders and things like XOR would benefit quite a bit from going 4-high where stages could be cascaded using little more than vias.

 

[JayNor]

Intel presented on 2d materials at IEDM in Dec. Any new info presented on 2d materials?

 

[Diogene7]

There are other major limitations to stacking more than 2 layers in CFET, specifically routing. Each transistor needs 3 contacts (source, drain, gate) and sometimes transistors can share multiple. CFET works because most transistors in CMOS architecture are paired so they can share contacts (usually the source and the gate). If you start adding 3 or 4 transistors in a stack, you quickly run out of surface area for all the contacts to connect to all the transistors in a stack. When transistors in a stack aren't paired, it also becomes challenging (but surmountable) to vertically isolate their gates from each other.

3DNAND is a special case because little routing is needed. Each stack shares 1 source and 1 drain and the gates are shared by thousands of transistors in a plane, each. Even still, the staircase structures needed to contact each NAND gate are complex and non-trivial to manufacture.

Mono CFET also presents challenges to create the nanosheets and then etch deep enough that will probably limit the number of ribbons in a stack for a while. Sequential CFET with several layers of interconnects between the ribbons would be a possibility for solving both the routing problems and the stack pattern problems, but at that point, you're looking at something more in common with Foveros/active interposer than a monolithic chip solution.

Bottom line, although possible, I don't see it very likely to move beyond a stack of 2 paired transistors of CFET quickly.

I agree with your assessment of Forksheet. It's basically GAAFET with a dielectric to split each fin in half so that both PMOS and NMOS operate on the same fin.

I'm a former technical trainer in semiconductor manufacturing. I trained new hires on process flow and capabilities. I've been writing articles on medium about finfet, gaafet and cfet for a more general audience. I won't link them, here, but you can look me up.

I don’t really understand why so much exponential technical and financial resources are allocated to attempt to maybe gain low performance and low power efficiency incremental improvements (10% / 15%) on a technology, like silicon transistors, that is close to reaching its limit and is a dead end, versus re-allocating those resources to significantly invest in next generation computing technologies like spintronics related technologies (MRAM, Intel MESO concept, French R&D Spintec FESO concept,…) as it seems that could improve power efficiency from 5x to 30x with plenty new opportunities (better suited for AI,…) which, at this point (2023) seems quite obviously (to myself at least) the next step.

The development of CFET is much too expensive compared to the opportunities that spintronic related technologies would provide : CFET is unfortunately delaying a much better technology (spintronic technologies).

Also I don’t understand that at this stage DARPA and the US government (US CHIPS Act) still don’t yet make it a top priority fin order that the US regain its technological leadership…

 

[Diogene7]

I don’t really understand why so much exponential technical and financial resources are allocated to attempt to maybe gain low performance and low power efficiency incremental improvements (10% / 15%) on a technology, like silicon transistors, that is close to reaching its limit and is a dead end, versus re-allocating those resources to significantly invest in next generation computing technologies like spintronics related technologies (MRAM, Intel MESO concept, French R&D Spintec FESO concept,…) as it seems that could improve power efficiency from 5x to 30x with plenty new opportunities (better suited for AI,…) which, at this point (2023) seems quite obviously (to myself at least) the next step.

The development of CFET is much too expensive compared to the opportunities that spintronic related technologies would provide : CFET is unfortunately delaying a much better technology (spintronic technologies).

Also I don’t understand that at this stage DARPA and the US government (US CHIPS Act) still don’t yet make it a top priority fin order that the US regain its technological leadership…

 

[InvalidError]

I don’t really understand why so much exponential technical and financial resources are allocated to attempt to maybe gain low performance and low power efficiency incremental improvements (10% / 15%) on a technology, like silicon transistors, that is close to reaching its limit and is a dead end, versus re-allocating those resources to significantly invest in next generation computing technologies like spintronics related technologies

Most of spintronics-related stuff besides data storage only works either as isolated transistors or require cryogenic temperatures, which means it may never make it to the consumer market no matter how much money gets poured into R&D.

CFET on the other hand is just stacking already well-understood and mature stuff in new ways. Going with fully 3D chip layouts is simply logical evolution.

 

[Diogene7]

Sure I understand that CFET is a much less risky path as it is a continuous improvement of a well known technology.

That said, silicon transistors is still a dead end (too power hungry): it is like persisting to invest to develop very expensive Internal Combustion Engine (ICE) when it is clear that the long term future (10+ years) is Electric Vehicules (EVs). And Tesla has proven early that it is possible to achieve EVs HVM by commiting significant resources.

Although spintronic technologies are still in early days, there is a tremendous growing R&D pool worldwide, and if any CFET (and subsequent) silicon transistor R&D resources were re-allocated to spintronic, there is no doubt in my mind that it would fastrack the advent of spintronics related technologies (that is badly needed) like Intel MESO / Spintec FESO that seems better suited to both AI and digital logic.

European research center IMEC, that develop many of the semiconductor manufacturing tools, has very active programs around spintronics.

My belief is that we are currently at the early days of the the transition from silicon transistor to spintronic related technologies, like the previous transition in the 1950/1960 from vacuum tubes to silicon transistors. This will become more obvious in the next 5 to 10 years (between 2030 and 2035).

But again, I do understand it is a much riskier path, and it has to be a whole industry effort as one company alone can’t do everything.

 

[InvalidError]

If you want to make high-density spin-based computing circuitry, you will need manufacturing technology far more advanced than CFET and that will take decades before becoming economically viable on a mass scale if ever.

 

[Diogene7]

CFET transistors are planned for somewhere between 2030 and 2040, and probably also require some tool improvements and/or new tools.

So I think I would somewhat disagree on this because there are already some existing tools that have been developed for MRAM manufacturing : it is likely that, at least some, of those tools could be re-used and improved for spin related technologies.

That is the reason why I believe that as a 1st step, MRAM should first be scale-up to high HVM for depreciating those tools and make them more common, and generate revenue to further invest in R&D to improve those tools. Then a few years later, it would lower the cost to migrate to other spintronic related technologies.

Let assume it would cost (ex: 100) to develop CFET, then I would agree that it will be more expensive to develop spintronic related technologies (ex: 120 / 150) but overall, the benefits will also be much, much higher (much better power efficiency, NVM, start the transition to spintronic a decade earlier,…)

That is where incentives and the US CHIPS Act could play an important role by helping fund the cost gap between CFET / spintronic to accelerate the transition to spintronic related technologies.

For example, it could have granted funds to scale-up a HVM fab for 32Gbits+ NVM MRAM in a way that makes MRAM reasonably competitive with other entrenched volatile DRAM.

It is the same principle than the transition from ICE vehicules to EV, or from fossil fuel to solar photovoltaics energy : there is a need of some incentives at first, to help the technology become cost competitive.

Alternatively, without incentives, it will likely take much longer (ex: OLED versus LCD).

 

[InvalidError]

CFET transistors are planned for somewhere between 2030 and 2040, and probably also require some tool improvements and/or new tools.

CFET doesn't require any special tech, it can be done on the same equipment used to make GAA/ribbon FETs today. The only thing it changes is the additional process steps required to build up additional active layers. The main reason they aren't using it already is because they haven't reached the practical limits of planar scaling yet. You don't want to lengthen the manufacturing process by dozens of steps to add a second or third active layer before it becomes absolutely necessary.

So I think I would somewhat disagree on this because there are already some existing tools that have been developed for MRAM manufacturing : it is likely that, at least some, of those tools could be re-used and improved for spin related technologies.

As I wrote in my previous replay, spintronics doesn't work at room temperature for anything besides data storage. What has been developed for MRAM is unlikely to be of any use for anything else in the mainstream.

 

[Diogene7]

CFET doesn't require any special tech, it can be done on the same equipment used to make GAA/ribbon FETs today. The only thing it changes is the additional process steps required to build up additional active layers. The main reason they aren't using it already is because they haven't reached the practical limits of planar scaling yet. You don't want to lengthen the manufacturing process by dozens of steps to add a second or third active layer before it becomes absolutely necessary.

Yep, this makes sense. I agree that industry will avoid any unnecessary added steps until absolutely necessary to lower costs.

As I wrote in my previous replay, spintronics doesn't work at room temperature for anything besides data storage. What has been developed for MRAM is unlikely to be of any use for anything else in the mainstream.

I am not sure of that but I am wondering if you don‘t mistake spintronic with quantum computers ? Most spintronic related technologies works with technology that are related to Magnetic Tunnel Junction (MTJ), which works fine at room temperature and are already in use in MRAM, (which I would consider is in manufacturing for a growing niche at this stage, due to high costs, thus the need for incentives/funding to scale up manufacturing to help dropping the cost faster.

Also for example, European research center IMEC is already investigating p-bit (probabilistic bit) computing with technologies that are perfectly compatible with room temperature.

But for other concepts like Intel MESO, although real demonstrator have been shown, the performance was not yet good enough and there is still a need to find new materials with better performance… Thus the need for more research funding…

However for French R&D Lab Spintec FESO concept, I think at this stage it was indeed demonstrated only at low temperature (but not room temperature).

 

[InvalidError]

I am not sure of that but I am wondering if you don‘t mistake spintronic with quantum computers ? Most spintronic related technologies works with technology that are related to Magnetic Tunnel Junction (MTJ), which works fine at room temperature and are already in use in MRAM, (which I would consider is in manufacturing for a growing niche at this stage, due to high costs, thus the need for incentives/funding to scale up manufacturing to help dropping the cost faster..

MRAM relies on bulk magnetism to do its thing, which is trivial. The main challenges there are making it small enough to compete with DRAM on density and finding cost-effective manufacturing methods.

If you want to process information at GHz speeds using manipulation of polarized electron spin, you need to make each device much smaller, which means no more bulk magnetism to offset thermal noise that will interfere with polarization every step of the way . You want to make this stuff small and fast? I don't see that happening without cryogenic temperatures.

 

[Diogene7]

MRAM relies on bulk magnetism to do its thing, which is trivial. The main challenges there are making it small enough to compete with DRAM on density and finding cost-effective manufacturing methods.

Yes, I would agree that it is 2 important metrics to make it more competitive with DRAM. I don’t think it could be as cheap as DRAM, but if it could reach 10x DRAM price at same capacity, it would likely already open plenty new opportunities in terms of architecture / design tradeoffs.

If you want to process information at GHz speeds using manipulation of polarized electron spin, you need to make each device much smaller, which means no more bulk magnetism to offset thermal noise that will interfere with polarization every step of the way . You want to make this stuff small and fast? I don't see that happening without cryogenic temperatures.

There are many concepts with different trade-offs surrounding spintronics (or related to some kind of spintronic effect), like the Intel MESO concept or Spintec FESO concept, and they open new architecture opportunities.

So for some workloads, you may not need to do as many steps with spintronic than with silicon transistors and could come at the same result as fast, or nearly as fast but while consuming significantly less (which should be a top priority).

For example, it seems that Intel showed that Majority Gate logic was well suited for AI and could be done more efficiently with spintronic related technology / Intel MESO.