verilog

Forum discussion tagged with verilog.
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    Question can i make compile stage shorter in VCS (synopsys)?

    if i changed few lines from a specific verilog of design and now i want to recompile, can i compile just the related files or i need to compile the whole design again? im using VCS tool by synopsys.
    • asifvg1
    • Thread
    • hardware simulation vcs verilog
    • Replies: 2
    • Forum: Systems
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