3.73Ghz P4 2MB L2 Cache in Q3: 1066Mhz FSB

[Mephistopheles]

As an extra: The inquirer now reports a 3.6Ghz Prescott won't be around until 22nd August. This is, for the unsuspecting, Q3.

I think we should stop speculating when Intel will get what out. I get the impression they're on an ASAP basis anyway... So they'll get something out by the time they can get this something to work!

<i><font color=red>You never change the existing reality by fighting it. Instead, create a new model that makes the old one obsolete</font color=red> - Buckminster Fuller </i>

 

[endyen]

The Register is saying that will be a Dothan part. That would be some fast. Watch out Amd, Intel gona eat you.

 

[Mephistopheles]

My god, a 3.73Ghz Dothan on 1066Mhz FSB? In 2004? No, I seriously doubt that that would be possible. That would be the holy grail of processors in 2004. It would be a royal kick in AMD's a$$. Hard to believe...

If this baby is Dothan-based, it is more likely a fully-featured dual-core dothan @ 1.86Ghz and higher and improved FSB. This might... <i>might</i> be remotely possible in 2004, <i>if</i> it were a chip <i>that had already been considered</i> and therefore wasn't so far from completion.

Still sounds an awful lot like crazy talk to me, though. I'd love to believe it. We'll see, I guess.

What does seem to be the case is that Prescott is truly having problems. And I agree, it sounds suspicious that Intel suddenly has a doubled L2 cache in the wings for prescott for Q3, with increased FSB, while the standard 3.6Ghz, which had been promised for Q2, is now slated for a 22nd August release.

Something just doesn't feel right. We're missing part of the story...

<i><font color=red>You never change the existing reality by fighting it. Instead, create a new model that makes the old one obsolete</font color=red> - Buckminster Fuller </i>

 

[HardWareBoss]

More fuel for the fire. To keep everyone quessing as to whats coming next.

 

[endyen]

Check this out. http://www.theregister.co.uk/2004/05/12/intel_desktop_dothan/ They say single core, and 3.73Ghz.

 

[darko21]

WOW!! if that is true, that would be a huge break through for intel. even the anandtech mention 3.6giz pentium m in intels road map.

If true this is a break though for intel.

If I glanced at a spilt box of tooth picks on the floor, could I tell you how many are in the pile. Not a chance, But then again I don't have to buy my underware at Kmart.

 

[imgod2u]

It not even a size vs lantency issue with prescott.Never a increase in size result in a linear increase in latency.

8KB to 16 KB 2 cycle to 4 cycle.
512 KB to 1MB 12 cycle to 25 cycle.

Almost a perfect linear increase in size and lantency.I know longer stage result in more cache latency.Larger path to the ALU FPU may have also decrease is performance.

I think that a deep probleme in the circuit on all of those reason.

Pipeline length would not affect the cache latency as it has nothing to do with instruction latency (from the point after you fetch it). I'm guessing Intel relaxed on the cache latency intentionally in order to make the processor scale higher (only to hit a brick wall with thermal problems).

"We are Microsoft, resistance is futile." - Bill Gates, 2015.

 

[BigMac]

They say single core, and 3.73Ghz.

They say <b>they think</b> it's single core Dothan. Quote from the article itself:

The odd thing is that the regular 3.73MHz part not only contains 2MB of L2 cache but has been described as carrying the model number 720. Both factors suggest that the part is based on 'Dothan'

It's all speculation at this point and the article is just speculating as the discussion here.


BigMac

<A HREF="http://www.p3int.com/product_center_NWO_The_Story.asp" target="_new">New World Order</A>

 

[juin]

Pipeline length would not affect the cache latency as it has nothing to do with instruction latency (from the point after you fetch it). I'm guessing Intel relaxed on the cache latency intentionally in order to make the processor scale higher (only to hit a brick wall with thermal problems).


Delay in the back end and front end have to be about equal.Like you say if the cache pipeligne are too large the overall delay of the front end will be higher and as usual the slowest pipeligne will give the frequency.I thing that come to me was P4 was using speculation load for the ALU and not for the FPU.I wonder if prescott use standart fetching for the ALU and FPU.

Personnaly i think that a bad choice.

i need to change useur name.

 

[Mephistopheles]

The inquirer posted an e-mail clarifying this a little bit.

Apparently, the Tejas development team had come up with several new features/layouts, including the 1066Mhz FSB and 2MB L2 cache. Now that Tejas has been definitely canned, this means that some of Tejas' features might show up in prescott much earlier, so they didn't waste money developing these new features.

In any case, Prescott will get a boost, which can only be good. Hopefully, it will mature into a respectable product <i>with 64-bit support.</i>

<i><font color=red>You never change the existing reality by fighting it. Instead, create a new model that makes the old one obsolete</font color=red> - Buckminster Fuller </i>