News Adata Overclocks Its DDR5 Module to 8118 MT/s

[Admin]

Adata's pre-production DDR5 memory module hits 8118 MT/s.

Adata Overclocks Its DDR5 Module to 8118 MT/s : Read more

 

[wifiburger]

lol....
that 8118MT/s might as well be DDR4 4000 or lower

50tcl cycles + 50trcd cycles, 100 cycles to get in/out data + Gear4 for the addressing

let's compare to bdie 4000 , 16tcl + 16trcd to get in/out data, yeah 32cycles at 4000MT/s

see the problem here ? 3x the latency

 

[TJ Hooker]

lol....
that 8118MT/s might as well be DDR4 4000 or lower

50tcl cycles + 50trcd cycles, 100 cycles to get in/out data + Gear4 for the addressing

let's compare to bdie 4000 , 16tcl + 16trcd to get in/out data, yeah 32cycles at 4000MT/s

see the problem here ? 3x the latency

RAM timings are specified in clock cycles. A clock cycle at 8118 MT/s takes ~half as long as one at 4000 MT/s. So as CL of 50 at 8000 MT/s is equivalent to a CL of 25 at 4000 MT/s in real latency (12.5 ns). So first word latency is ~1.5x, not 3x. With an 8n prefetch, it takes 54 cycles to complete a single data burst (13.5 ns at 8000 MT/s), assuming the row was already open. The DDR4 would take 20 cycles, which would be 10ns at 4000 MT/s. So looking at it that way, the latency is now only 35% higher.

 

[wifiburger]

RAM timings are specified in clock cycles. A clock cycle at 8118 MT/s takes ~half as long as one at 4000 MT/s. So as CL of 50 at 8000 MT/s is equivalent to a CL of 25 at 4000 MT/s in real latency (12.5 ns). So first bit latency is ~1.5x, not 3x. With an 8n prefetch, it takes 54 cycles to complete a single data burst (13.5 ns at 8000 MT/s), assuming the row was already open. The DDR4 would take 20 cycles, which would be 10ns at 4000 MT/s. So looking at it that way, the latency is now only 35% higher.

you're calculation kinda make sense, but DDR5 is forced into Gear4 for addressing & commands

if it was only 35% higher, we would of not got these early leaks on DDR5 showing 140ns for latency vs 40ns, 70ns DDR4 numbers.

 

[TJ Hooker]

if it was only 35% higher, we would of not got these early leaks on DDR5 showing 140ns for latency vs 40ns, 70ns DDR4 numbers.

I'm not sure which leaks you are referring to, but in general if the leaks are using DDR5 running at JEDEC spec then their timings are going to be pretty loose (as seems to always be the case with JEDEC timings). E.g. for DDR4 4800 the CL would be 40. Unless they're comparing it to DDR4 that's also running at JEDEC spec, it's not really a fair comparison. The max JEDEC speed for DDR4 is 3200 MHz as far as I know, with a CL of 20. Comparing those two, the difference in real CL should be 33%, at least on paper.