Advanced Micro Devices May Be Acquired – Analyst

[zeezee]

It is a design decision... and a change. What we are arguing here is what is the threshold for considering it new.... so yes, more cache would be an architecturally different processor.

Well, we all know that Conroe and Dothan aren't the same processor, so there is something different between them. The question is are these differences substantial enough to qualify as "a New Architecture". Pitty, we don't have official guidelines to define what is an architectural change, what is not but you put it nicely a few posts ago, it is only a matter of definition (and a bit of personal perception).

However C2D over P3 was a bit more than just more cache.

Jeez. I never said C2D was a P3 with a bigger cache. I said Conroe was a fine tuned Banias/Dothan (let's add 2xDothan - Yonah).

On the contrary, I believe, there is a big structural improvement between P3 and Core structures. New power management features, 64-Bit, cache management+cache speeds, completely redesigned integer and FP units.. These are (for me) substantial enough to qualify a new architecture.

While we are at it, I don't consider MMX, 3DNOW, SSEx (the instruction set, not the calc units which I considerd in FPU above) and new 64 Bit Instructions+Registers as a revolutunary improvement since x86 became a high level language after P-Pro (like you mentioned in one of your posts). These are relatively simple instruction decoding unit redesigns.

 

[zeezee]

I made no personal attack nor insult... simply stated your argument is flawed.... how is that insulting.

By calling what I wrote BS and making an effort to educate me.

But you deserve full credit an apology from me. Compared to the overall tone in these boards, what you said above sounds like a complement

 

[dasickninja]

That's still a bit insulting to Intel Israel. It bears similarities, but its far more than even a fine tunned P3.

 

[zeezee]

That's still a bit insulting to Intel Israel. It bears similarities, but its far more than even a fine tunned P3.

I'll repeat again. I did not say Conroe was an improved P3. I said Conroe was an improved Banias/Dothan in which case it's not an insult to Israel but a complement for being the designer of Banias.

And insult/no insult over a piece of silicon. Aren't we getting a bit too "sentimental" about this?

 

[zeezee]

Frankly, the last real revolutionary change in x86 architecture we the implementation of OOOe engines, since this everything is more or less a tweak of that concept. Since PPro, the general gist is fetch, align, decode, reorder, exectue, and retire.... PII did this, as well as K6 ... even today Barcelona will do this just as Core 2 Duo does this....

Agreed. I also believe, there is a big unused potential in this OOOe area. Imagine a big-enough buffer between the instruction decoder and execution units where more micro-codes are stored, increasing the odds of OOOe and a smarter cache logic to provide the memory operands. If we go one step further, instead of branch prediction, memory operands can be obtained from both branches and stored in the cache. This way, calc units would almost never be idle.

I don't know, maybe I'm dreaming but designers seem to like the idea of brutally increasing the cache sizes instead of working on logic improvements.

 

[1Tanker]

Frankly, the last real revolutionary change in x86 architecture we the implementation of OOOe engines, since this everything is more or less a tweak of that concept. Since PPro, the general gist is fetch, align, decode, reorder, exectue, and retire.... PII did this, as well as K6 ... even today Barcelona will do this just as Core 2 Duo does this....

Agreed. I also believe, there is a big unused potential in this OOOe area. Imagine a big-enough buffer between the instruction decoder and execution units where more micro-codes are stored, increasing the odds of OOOe and a smarter cache logic to provide the memory operands. If we go one step further, instead of branch prediction, memory operands can be obtained from both branches and stored in the cache. This way, calc units would almost never be idle.

I don't know, maybe I'm dreaming but designers seem to like the idea of brutally increasing the cache sizes instead of working on logic improvements.It's just a means to an end. Who cares "how" Intel got C2D to perform as well as it does... the important thing is...."it does perform well". The increased cache basically elliminated the "problems" associated with the FSB. Even though it's just a dumb cache increase, it did a world of good. I you have a sport compact car, and don't have room under the hood for a 6 banger, throw in the 4-cylinder, and put a turbo on it...end of problem. Sometimes the easiest and most obvious fixes are the best.

 

[gOJDO]

I'll repeat again. I did not say Conroe was an improved P3. I said Conroe was an improved Banias/Dothan in which case it's not an insult to Israel but a complement for being the designer of Banias.

And insult/no insult over a piece of silicon. Aren't we getting a bit too "sentimental" about this?

Core2 is a new architecture and is much more than an improved Dothan.
Core2 has much more improvements over Dothan or over Banias, than Banias or Dothan has over any P3. Dothan is not only a shrink of Banias with more L2, but it has architectural improvements(not a new architecture, but some parts redesigned). Also there is a big difference between P3 Katmai and P3 Tualatin, although both appear similar on paper.

 

[r0x0r]

IBM + AMD = 29nm... Well, maybe not straight away.

My personal feelings are that Intel would hope AMD + IBM will never happen.

 

[r0x0r]

too late 48 mb cache is here.

8O 8O 8O

(Picks up jaw from floor)...

Which gives a better performance increase; more cores or more cache? I would presume that more cache would be ideal if energy efficiency and consumption is a concern.

Edit: Spelling error

 

[Sirfiroth]

Agreed. I also believe, there is a big unused potential in this OOOe area. Imagine a big-enough buffer between the instruction decoder and execution units where more micro-codes are stored, increasing the odds of OOOe and a smarter cache logic to provide the memory operands. If we go one step further, instead of branch prediction, memory operands can be obtained from both branches and stored in the cache. This way, calc units would almost never be idle.

I don't know, maybe I'm dreaming but designers seem to like the idea of brutally increasing the cache sizes instead of working on logic improvements.

IMHO You are on the right track.
If you could eliminate invalid states in the cache, cache snoops, wouldn't it speed up the process considerably?
does this make any sense?
_____________________
“When multiple competing theories are equal in other respects, the principle recommends selecting the theory that introduces the fewest assumptions and postulates the fewest hypothetical entities”. ~ William of Ockham.

 

[zeezee]

Core2 is a new architecture and is much more than an improved Dothan.
Core2 has much more improvements over Dothan or over Banias, than Banias or Dothan has over any P3. Dothan is not only a shrink of Banias with more L2, but it has architectural improvements(not a new architecture, but some parts redesigned). Also there is a big difference between P3 Katmai and P3 Tualatin, although both appear similar on paper.

Well, No. Core 2 and Dothan are essentially the same product, just labeled incorrectly. Some say it was because packaging line workers in Intel didn't speak good Hebrew, others say it's a conspiracy against AMD.

As for P3 Katmai and Tualatin.... the same. Only the names were the winners of the "Impossible to spell and Pronounce Names Competition". There are also rumors around that these two names were taken from ancient Klingon but Lt. Worf denied them.

 

[zeezee]

If you could eliminate invalid states in the cache, cache snoops, wouldn't it speed up the process considerably?
does this make any sense?

With todays microprocessor architecture, sure it would speed up the process.

However, the entire cache concept was a quick and dirty solution to the slow memory (or faster processors, pick one) problem. Now, the cache system reached its practical limits and causing complications in multi-processor environments like cache snooping, invalid cache content, etc.

I believe, long term, engineers should solve the initial problem and produce financially viable fast memories to get rid of the cache or at least reduce its size rather than creating a memory sub-system with the cache to solve the problems of an earlier solution.

OMC was a good step towards it. Athlons are less cache-sensitive compared to P4's or Cores.

 

[CaptRobertApril]

Geez, I take a day off to procreate or at least go through the motions, and there are five thousand posts to go through in this thread. 🙁 Anyway, lemme just make one lil statement to try and bring this thread back to the title... Referring to AMD's recent stock "spikes", the after hours is down and if you back up the stock chart from one week to one year, and you'll see that AMD stock has obeyed the laws of physics. It took a huge fall from a skyscraper and then when the dead body landed it bounced up a millimeter or two a couple of times... :lol:

 

[halbhh]

If you could eliminate invalid states in the cache, cache snoops, wouldn't it speed up the process considerably?
does this make any sense?

With todays microprocessor architecture, sure it would speed up the process.

However, the entire cache concept was a quick and dirty solution to the slow memory (or faster processors, pick one) problem. Now, the cache system reached its practical limits and causing complications in multi-processor environments like cache snooping, invalid cache content, etc.

I believe, long term, engineers should solve the initial problem and produce financially viable fast memories to get rid of the cache or at least reduce its size rather than creating a memory sub-system with the cache to solve the problems of an earlier solution.

OMC was a good step towards it. Athlons are less cache-sensitive compared to P4's or Cores.

I was just reading how the IBM says it's eDram will "double" cpu performance. IBM has a lot of credibility, so there's probably some real gain to be had there. While the idea is bigger and faster cache, it occurs to me the obvious: this stuff is much faster than DDR2, and perhaps will see something there also in time.

 

[qcmadness]

Well, No. Core 2 and Dothan are essentially the same product, just labeled incorrectly. Some say it was because packaging line workers in Intel didn't speak good Hebrew, others say it's a conspiracy against AMD.

As for P3 Katmai and Tualatin.... the same. Only the names were the winners of the "Impossible to spell and Pronounce Names Competition". There are also rumors around that these two names were taken from ancient Klingon but Lt. Worf denied them.

Pentium M => Banias, Dothan
Core Duo => Yonah
Core 2 Duo => Merom

Core 2 is not Dothan

 

[CaptRobertApril]

OMG! AMD JUST DROPPED $6 TO $8.84!

oh, i must be dreaming... market is closed today.

:lol:

 

[qcmadness]

OMG! AMD JUST DROPPED $6 TO $8.84!

oh, i must be dreaming... market is closed today.

:lol:

Once I thought of the NYSE, but I have noticed the holiday already.

I am now having Lunar New Year Holiday for 4 days 😀

 

[CaptRobertApril]

Once I thought of the NYSE, but I have noticed the holiday already.

I am now having Lunar New Year Holiday for 4 days 😀

Happy new year! I'm so happy that this year is finally here. This is my year! The year of the PIG! :lol:

 

[qcmadness]

Once I thought of the NYSE, but I have noticed the holiday already.

I am now having Lunar New Year Holiday for 4 days 😀

Happy new year! I'm so happy that this year is finally here. This is my year! The year of the PIG! :lol:

Happy new year to you also 😀

 

[zeezee]

Well, No. Core 2 and Dothan are essentially the same product, just labeled incorrectly. Some say it was because packaging line workers in Intel didn't speak good Hebrew, others say it's a conspiracy against AMD.

As for P3 Katmai and Tualatin.... the same. Only the names were the winners of the "Impossible to spell and Pronounce Names Competition". There are also rumors around that these two names were taken from ancient Klingon but Lt. Worf denied them.

Pentium M => Banias, Dothan
Core Duo => Yonah
Core 2 Duo => Merom

Core 2 is not Dothan
With all due respect, is this the only problem that you see with my post?

 

[qcmadness]

With all due respect, is this the only problem that you see with my post?

As for P3 Katmai and Tualatin.... the same. Only the names were the winners of the "Impossible to spell and Pronounce Names Competition". There are also rumors around that these two names were taken from ancient Klingon but Lt. Worf denied them.

Katmai: off-die 512KB half-speed L2 cache
Tualatin: on-die 512KB full-speed L2 cache

Katmai => Coppermine => Tualatin.

 

[gOJDO]

Well, No. Core 2 and Dothan are essentially the same product, just labeled incorrectly.

Following your logic Dothan is essentially the same product as Pentium Pro, which means that Core2 and Pentium Pro are essentially same products. Considering the differences between Pentium Pro and Core2 and according to your logic, we can conclude with great certainty that Pentium Pro is essentially the same product as 8086. So, 8086 is essentially the same product as Core2, but are named differently because some noob-workers have not finished their primary school and are unable to read Core2 properly. :roll:

 

[gOJDO]

Katmai: off-die 512KB half-speed L2 cache
Tualatin: on-die 512KB full-speed L2 cache

Katmai => Coppermine => Tualatin.

If you skip the frequencies, overclockability, power efficiency, production process, pacakge, etc... some differences between P3 Katmai and Tualatin:
- redesigned pipeline
- improved OOO
- full-speed on-die L2(vs half-speed, not on-die)
- 256bit 8-way L2(vs 64bit 4-way L2)
- 8 entries bus queue(vs 4 entries)
- 8 x 32Bytes read buffer(vs 4 x 32Bytes)
- 4 x 32B write buffer(vs 1 x 32B)
- Hardware data prefetching
- FSB 133MHz(vs 100MHz)

 

[zeezee]

With all due respect, is this the only problem that you see with my post?

As for P3 Katmai and Tualatin.... the same. Only the names were the winners of the "Impossible to spell and Pronounce Names Competition". There are also rumors around that these two names were taken from ancient Klingon but Lt. Worf denied them.

Katmai: off-die 512KB half-speed L2 cache
Tualatin: on-die 512KB full-speed L2 cache

Katmai => Coppermine => Tualatin.
Yes. That would be my conclusion as well.

 

[zeezee]

Well, No. Core 2 and Dothan are essentially the same product, just labeled incorrectly.

Following your logic Dothan is essentially the same product as Pentium Pro, which means that Core2 and Pentium Pro are essentially same products. Considering the differences between Pentium Pro and Core2 and according to your logic, we can conclude with great certainty that Pentium Pro is essentially the same product as 8086. So, 8086 is essentially the same product as Core2, but are named differently because some noob-workers have not finished their primary school and are unable to read Core2 properly. :roll:
Naravno brate. Since 6502, they are all the same processor