The way I saw it explained for DDR2 is that it maintained sending on both the rising and falling edges, but then halved the DRAM clock relative to the interface clock. Hence, the rate at which data is being sent is 4x per tick of the DRAM clock. I'm not sure exactly where DDR3 got another doubling, unless it was by halving the DRAM clock yet again.quad data rate means 400mhz = 1600mt/s (QDR is mostly seen on GPUs)
I think you're saying that only because you assume they could've kept scaling up frequencies at the current channel data width. I'm not sure that's true.ddr5 split 64bits into two 32bit streams (aka qdr or dual channel at half bandwith), no bandwith benefit, just latency related..