OfficialG3 :
so basically amd is re-living intel's old C2Q concept with 1 die but with more cores crammed to it ?
One CPU substrate (package) with two dies on it. The first dual-core P4 (Pentium D) were also built in a similar way.
In the P4/C2Q days, the dies were interconnected by sharing the FSB like a dual-socket system would. I wonder what sort of interconnect there would be between two R7-like dies to create that 16C32T chip. Getting sufficient bandwidth to avoid cross-die bottlenecks will require a lot more than sacrificing a handful of PCIe/USB/SATA ports. I guess that could be what the areas of what looks like a high density of small IO macros are for in the middle of the bottom edge on Ryzen's die image. Flip the die 180 degrees and it looks like a block of out ports lined up with the other die's in ports with a single control macro in the middle for the whole thing, unlike the PCIe/GPIO macros on opposite corners which have a control block for every 2/4 lanes.