AMD CPU speculation... and expert conjecture

[sarinaide]

I would target HD7770 performance, then its truely mainstream low end and 1080 ready. A while ago they said AMD would double the SP of Trinity that's a hair over 750 Stream processors for the top end part. current parts are 8 ROP's and 48 TMU's may need that and the memory bus bumped.

To double the SPs they'd have to jump to like 2Billion transistors (approx 125mil Transistors per CU). Couple that with the power draw of SR you'd have over a 200W CPU. Not likely without a hefty downclock of the CPU cores.

You're seeing why for PS4 they had to drop in the much smaller Jaguar cores to offset the 18 CU.

Adding a bunch of SPs to a current APU will not increase performance all that much because it is probably already bandwidth-limited. The APUs can use up to a 128 bit DDR3-2133 interface, good for 33.3 GB/sec. The HD 7750 with a 128 bit 1.125 GHz GDDR5 interface is good for 72 GB/sec. That's a pretty big difference in bandwidth. You'd need to add some L4/eDRAM or add additional memory channels to get much more performance out of the GPU part of the APU. That's also why the Jaguar setup in the PS4 has the supplemental GDDR5.

But it will help HSA which AMD is pushing. eDRAM is out of the question unless we find out it is like a console SoC but since FM2+ is socketed thats out of the question and it looks like no GDDR5 embeds either so AMD will need to find 20-30GB/s bandwidth out of GCN, improved IMC and maybe quad channel support or some trick AMD has learned along the way that miracle cures bandwidth woes.

 

[esrever]

GCN is already more bandwidth efficient than VLIW. Only really need to get it in a chip first. The next step would be DDR4 after that.

 

[palladin9479]

"Embedded GDDR5" was always a pipe dream. Any significant (read: usable) quantity of DRAM takes up too much die real estate that's already at a premium. Now it's possible to include some on-chip GDDR5 memory, gets kinda expensive which might defeat the purpose of the whole thing. Best bet would be to create the option to include a second bus and a special slot on the motherboard for 128-bit GDDR5 (256-bit if they can get the pin density on SO-DIMM). That way mobo manufacturers would have the option to either soldier on 1GB of GDDR5 or include the slot so that the user can add it on their own, or just not include it and package it as a "value" motherboard. It would be similar to the old days of L2 "stick cache", if people can remember those.

 

[JAYDEEJOHN]

This looks good for lowering BW
DX12 anyone?
http://software.intel.com/en-us/articles/a-sort-based-deferred-shading-architecture-for-decoupled-sampling

 

[de5_Roy]

AMD Changes Attitude Towards Android: Set to Support the Platform.
AMD Fusion Chips for Tablets Set to Support Android OS
http://www.xbitlabs.com/news/mobile/display/20130605200013_AMD_Changes_Attitude_Towards_Android_Set_to_Support_the_Platform.html

moar kabini
http://www.anandtech.com/show/7033/computex-2013-spot-the-desktop-kabini


AMD Continues Assembling Dream Team: Sean Pelletier from NVIDIA Tech Marketing to Join, Update: He's back at NVIDIA
http://www.anandtech.com/show/6967/amd-continues-assembling-dream-team-sean-pelletier-from-nvidia-tech-marketing-to-join

 

[sarinaide]

"Embedded GDDR5" was always a pipe dream. Any significant (read: usable) quantity of DRAM takes up too much die real estate that's already at a premium. Now it's possible to include some on-chip GDDR5 memory, gets kinda expensive which might defeat the purpose of the whole thing. Best bet would be to create the option to include a second bus and a special slot on the motherboard for 128-bit GDDR5 (256-bit if they can get the pin density on SO-DIMM). That way mobo manufacturers would have the option to either soldier on 1GB of GDDR5 or include the slot so that the user can add it on their own, or just not include it and package it as a "value" motherboard. It would be similar to the old days of L2 "stick cache", if people can remember those.

About 30-40 Pages back I posted links to rumoured adaptations of Kaveri which included Pentium 2 style PCI connect SoC's, to BGA SoC's like the PS4 to Motherboards with System Memory and special iGPU memory to motherboard embeded GDDR5. We know that Kaveri will have LGA and BGA all in ones so its still possible but for mainline LGA's it looks like we ar on system memory only.....sigh

 

[palladin9479]

Completely off topic but has anyone else seen the new SPARC T5 CPU that Oracle released. It's a monster, pretty much crush's IBM's Power7 and is cheaper to boot.

http://www.spec.org/cgi-bin/osgresults?conf=cpu2006

Search by CPU for CPU2006. T5 for the Oracle and Power 7 for the IBM. A single T5 is a 16 core chip where each core can handle 8 threads and is clocked at 3.6Ghz, has eight memory channels (per chip) and four 10Gbe circuits. You usually buy a dual socket solution but they offer quad and eight socket solutions along with single socket blades. No published M series data which is the big iron mainframe class systems.

Crazy HPC performance.

 

[gamerk316]

No, You didn't do your homework. PhysX could run better on a CPU than it would CUDA cores. PhysX is a marketing scheme. I like Nvidia, I'm just sick of all this forced ideas on how gaming should be. If I could afford it, I'd buy a 780 right now, not for PhysX, but because of the performance of the GPU and the capabilities it has with Adobe. Imo, Once Radeon fixes their drivers and makes stronger GPU cores, we're going to see massive improvements across the board and everyone will be neck and neck.

No it wouldn't; Physics, especially multi-object dynamics, KILLS CPU performance even worse then rendering does. Same reason AMD is doing the SAME EXACT THING now with OpenCL: Because Physics runs faster on the GPU.

Then again, lets ignore the guy whos actually worked with the API. Thats cool too.

 

[gamerk316]

I would target HD7770 performance, then its truely mainstream low end and 1080 ready. A while ago they said AMD would double the SP of Trinity that's a hair over 750 Stream processors for the top end part. current parts are 8 ROP's and 48 TMU's may need that and the memory bus bumped.

To double the SPs they'd have to jump to like 2Billion transistors (approx 125mil Transistors per CU). Couple that with the power draw of SR you'd have over a 200W CPU. Not likely without a hefty downclock of the CPU cores.

You're seeing why for PS4 they had to drop in the much smaller Jaguar cores to offset the 18 CU.

Adding a bunch of SPs to a current APU will not increase performance all that much because it is probably already bandwidth-limited. The APUs can use up to a 128 bit DDR3-2133 interface, good for 33.3 GB/sec. The HD 7750 with a 128 bit 1.125 GHz GDDR5 interface is good for 72 GB/sec. That's a pretty big difference in bandwidth. You'd need to add some L4/eDRAM or add additional memory channels to get much more performance out of the GPU part of the APU. That's also why the Jaguar setup in the PS4 has the supplemental GDDR5.

But throw in the cost of GDDR5, and its higher latency (which in my mind makes it very ill-suited for main memory), and you see the issues with using it as the primary form of system RAM. Hence the flaw with the HSA approach: You either are going to have to have its performance hobbled by memory speeds, or have a VERY expensive platform due to the costs of GDDR RAM.

Intel/AMD have done a good job hiding RAM's effect on system performance for a while now, but now that we are moving to having GPUs on the die, I don't think that can happen for any longer. Time to re-think the memory subsystem, prehaps?

 

[gamerk316]

This looks good for lowering BW
DX12 anyone?
http://software.intel.com/en-us/articles/a-sort-based-deferred-shading-architecture-for-decoupled-sampling

Completely off topic but has anyone else seen the new SPARC T5 CPU that Oracle released. It's a monster, pretty much crush's IBM's Power7 and is cheaper to boot.


Search by CPU for CPU2006. T5 for the Oracle and Power 7 for the IBM. A single T5 is a 16 core chip where each core can handle 8 threads and is clocked at 3.6Ghz, has eight memory channels (per chip) and four 10Gbe circuits. You uhttp://www.spec.org/cgi-bin/osgresults?conf=cpu2006sually buy a dual socket solution but they offer quad and eight socket solutions along with single socket blades. No published M series data which is the big iron mainframe class systems.

Crazy HPC performance.

Say what you will about Oracle, but they know their market. Thing is designed to crush massively-parallel workloads.

 

[sarinaide]

I would target HD7770 performance, then its truely mainstream low end and 1080 ready. A while ago they said AMD would double the SP of Trinity that's a hair over 750 Stream processors for the top end part. current parts are 8 ROP's and 48 TMU's may need that and the memory bus bumped.

To double the SPs they'd have to jump to like 2Billion transistors (approx 125mil Transistors per CU). Couple that with the power draw of SR you'd have over a 200W CPU. Not likely without a hefty downclock of the CPU cores.

You're seeing why for PS4 they had to drop in the much smaller Jaguar cores to offset the 18 CU.

Adding a bunch of SPs to a current APU will not increase performance all that much because it is probably already bandwidth-limited. The APUs can use up to a 128 bit DDR3-2133 interface, good for 33.3 GB/sec. The HD 7750 with a 128 bit 1.125 GHz GDDR5 interface is good for 72 GB/sec. That's a pretty big difference in bandwidth. You'd need to add some L4/eDRAM or add additional memory channels to get much more performance out of the GPU part of the APU. That's also why the Jaguar setup in the PS4 has the supplemental GDDR5.

But throw in the cost of GDDR5, and its higher latency (which in my mind makes it very ill-suited for main memory), and you see the issues with using it as the primary form of system RAM. Hence the flaw with the HSA approach: You either are going to have to have its performance hobbled by memory speeds, or have a VERY expensive platform due to the costs of GDDR RAM.

Intel/AMD have done a good job hiding RAM's effect on system performance for a while now, but now that we are moving to having GPUs on the die, I don't think that can happen for any longer. Time to re-think the memory subsystem, prehaps?

Well with DDR4 at the cost of exponential bandwidth gains is the cost of much higher latencies so this is not a unknown concept. Simply put things respond better to bandwidth than latency. But i do agree memory sub systems need to be re adapted for changing times.

 

[colinp]

Pardon me if I'm lacking in technical know-how, but instead of GDDR5 or DDR4, wouldn't a far simpler and cheaper option be to put a triple or quad channel DDR3 memory controller into Kaveri?

 

[8350rocks]

A quad channel memory controller would drive up production costs for both APUs and MBs. It wouldn't be economically viable in their current business model. Could they do it cheaper than SB-E setups? Sure...but that segment isn't huge anyway. Most people don't want to shill out $700 for CPU/MB before they spend more money on the rest of the system. Granted there are some that do...but even if you got that down to $500 it would still be a radical up tick in market for AMD.

The benefits from quad channel memory are also not the same as DDR4 or GDDR5...you get marginally more bandwidth for roughly the same cost as adding DDR4 compatability. DDR4 is orders of magnitude more bandwidth, and thus far more effective than quad channel DDR3.

 

[gamerk316]

Well with DDR4 at the cost of exponential bandwidth gains is the cost of much higher latencies so this is not a unknown concept. Simply put things respond better to bandwidth than latency. But i do agree memory sub systems need to be re adapted for changing times.

But at the same time, aside from graphics, you don't NEED that much bandwidth to gain performance, hence why you see very minimal gains when using a discrete GPU as you pump up RAM speeds. At that point, the lower latency is actually more important then pure bandwidth, so you can keep the OS from hanging.

Odds are, we will see a general widening of the memory bus, rather then a high bandwidth, low latency standard being adopted.

 

[colinp]

A quad channel memory controller would drive up production costs for both APUs and MBs. It wouldn't be economically viable in their current business model. Could they do it cheaper than SB-E setups? Sure...but that segment isn't huge anyway. Most people don't want to shill out $700 for CPU/MB before they spend more money on the rest of the system. Granted there are some that do...but even if you got that down to $500 it would still be a radical up tick in market for AMD.

The benefits from quad channel memory are also not the same as DDR4 or GDDR5...you get marginally more bandwidth for roughly the same cost as adding DDR4 compatability. DDR4 is orders of magnitude more bandwidth, and thus far more effective than quad channel DDR3.

Any kind of memory controller other than dual channel DDR3 would drive up production costs. And AMD already have the technology available in their Opteron parts, but would have to create a DDR4 controller from scratch.

Not only that, but DDR4 quite simply isn't available at the moment, and until it is as ubiquitous as DDR3, will be far more expensive.

And when you say "orders of magnitude more bandwidth," which base are you working in? If you say that DDR4 is an order of magnitude faster than DDR3, you are saying 10x faster or more.

 

[8350rocks]

DDR3 bandwidth numbers:

http://en.wikipedia.org/wiki/DDR3_SDRAM

DDR4 info and bandwidth numbers:

http://en.wikipedia.org/wiki/DDR4_SDRAM

http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art3-DDR4-IssQ4-12.aspx

Note: DDR3 @ 2133 MHz is 17066.67 Mbps data bandwidth, while the synopsys article clearly states the maximum for DDR4 bandwidth is 230 Gbps.

So we are talking orders of magnitude more bandwidth.

Additionally...DDR4 is available, and could quickly be ubiquitous easily. However, the issue is that until DDR4 gets out of infancy, the performance difference over DDR3 isn't going to be terribly dramatic.

Furthermore, HMC is more likely to be the next iteration of memory beyond DDR4. Don't expect a DDR5 as it is getting increasingly more difficult to scale down DRAM.

http://hybridmemorycube.org/technology.html

HMC will be orders of magnitude more bandwidth than DDR4 and greater density, with likely similar or slightly lower power consumption.

Either way...taking quad channel memory into a MB for very slight performance gain makes less sense than going to a technology that would effectively accomplish far more in terms of remedying memory bandwidth issues.

@gamerk316:

Yes, latency becomes an issue at a point when bandwidth is in abundance. DDR4 will obviously be higher latency as DDR3 was over DDR2. However, I think the new memory bus idea you have is likely right in line with what would occur if/when HMC is adopted widespread.

 

[sarinaide]

Well with DDR4 at the cost of exponential bandwidth gains is the cost of much higher latencies so this is not a unknown concept. Simply put things respond better to bandwidth than latency. But i do agree memory sub systems need to be re adapted for changing times.

But at the same time, aside from graphics, you don't NEED that much bandwidth to gain performance, hence why you see very minimal gains when using a discrete GPU as you pump up RAM speeds. At that point, the lower latency is actually more important then pure bandwidth, so you can keep the OS from hanging.

Odds are, we will see a general widening of the memory bus, rather then a high bandwidth, low latency standard being adopted.

I am thinking thats the case to, hopefully the SR cores and GCN cores will also address this issue in some part. Either way Kaveri is now officially on the clock and there is not intermediatory product and its kinda exciting so much so there has hardly been much talk on SR FX. With BF4 on the way I need Kaveri to give me that nice 50% boost as has been punted about which is very doable.

 

[sarinaide]

DDR3 bandwidth numbers:

http://en.wikipedia.org/wiki/DDR3_SDRAM

DDR4 info and bandwidth numbers:

http://en.wikipedia.org/wiki/DDR4_SDRAM

http://www.synopsys.com/Company/Publications/SynopsysInsight/Pages/Art3-DDR4-IssQ4-12.aspx

Note: DDR3 @ 2133 MHz is 17066.67 Mbps data bandwidth, while the synopsys article clearly states the maximum for DDR4 bandwidth is 230 Gbps.

So we are talking orders of magnitude more bandwidth.

Additionally...DDR4 is available, and could quickly be ubiquitous easily. However, the issue is that until DDR4 gets out of infancy, the performance difference over DDR3 isn't going to be terribly dramatic.

Furthermore, HMC is more likely to be the next iteration of memory beyond DDR4. Don't expect a DDR5 as it is getting increasingly more difficult to scale down DRAM.

http://hybridmemorycube.org/technology.html

HMC will be orders of magnitude more bandwidth than DDR4 and greater density, with likely similar or slightly lower power consumption.

Either way...taking quad channel memory into a MB for very slight performance gain makes less sense than going to a technology that would effectively accomplish far more in terms of remedying memory bandwidth issues.

@gamerk316:

Yes, latency becomes an issue at a point when bandwidth is in abundance. DDR4 will obviously be higher latency as DDR3 was over DDR2. However, I think the new memory bus idea you have is likely right in line with what would occur if/when HMC is adopted widespread.

HMC seems comensurate to AMD's HUMA evolutions, I like pioneering tech but since Kaveri is to early for DDR4 and thus way to early for HMC.

 

[noob2222]

deleted, internet ate my post. and where did the delete button go?

 

[sarinaide]

deleted, internet ate my post. and where did the delete button go?

Under BBCode tab

 

[noob2222]

thats stupid, it only shows up after another reply has been made. Toms: fix the forums.

 

[8350rocks]

Anybody see Tom's A10-6800k review? The power consumption is actually a bit lower with better performance. This bodes well for future efficiency improvements...though kabini is already a very efficient architecture in mobile space.

Wish we could see a Kaveri release date leaked sometime soon...my kids want a new PC for school/games...so I am eyeballing a kaveri setup. I would do Richland, but what they have now is ok, and with Kaveri 3-6 months out...I would rather wait and build on FM2+.

 

[esrever]

Pardon me if I'm lacking in technical know-how, but instead of GDDR5 or DDR4, wouldn't a far simpler and cheaper option be to put a triple or quad channel DDR3 memory controller into Kaveri?

nobody wants to have to stick 4 sticks of ram into an APU system in a laptop. Which is what AMD's main target is. The cost for a larger memory bus would be quite expensive too and probably drop yields. Its an expensive solution that probably won't get much use.

 

[Cazalan]

Search by CPU for CPU2006. T5 for the Oracle and Power 7 for the IBM. A single T5 is a 16 core chip where each core can handle 8 threads and is clocked at 3.6Ghz, has eight memory channels (per chip) and four 10Gbe circuits. You usually buy a dual socket solution but they offer quad and eight socket solutions along with single socket blades. No published M series data which is the big iron mainframe class systems.

Crazy HPC performance.

Always cool to see what the big boys are doing. Wonder how it will compare to the 16 core Ivy-E's coming out.

I found a cheat though in the fine print for T5.
"up to two threads running in each core simultaneously".

After recently reading an IBM power 7 article that's less than what IBM is doing. Their 4way SMT cores are running all 4 threads simultaneously.
http://www.dac.com/App_Content/files/49/DAC_Friedrich_20120603_slides_on_web.pdf
Slide 11

Anyhow that's just 1 aspect of the design. Sun must be making up the performance somewhere else.

 

[8350rocks]

1st kaveri chips "already delivered" per AMD. I am assuming ES's...but launch slated for early Q4 2013.

http://www.hardwareluxx.com/index.php/news/hardware/cpu/26584-computex-2013-amd-shows-qkaveriq-in-action.html

BGA Kaveri chips to have GDDR5 on board memory:

http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html