The Q6660 Inside :
Gah, what is with these flags and faces! Any explanation? On the topic of FM2b APUs, I think they may be waiting for 28nm FD-SOI from GF to ramp up.
It could be, the plans at GF are clearly future going in this respect, down to the 10nm node.
http://www.advancedsubstratenews.com/2013/04/gfs-two-flavors-of-fd-soi-kengeri-explains-exclusive-asn-qa/
(THAT IS AN EXCLUSIVE INTERVIEW WITH A TOP EXECUTIVE OF GF)
Besides porting a design from "planar" bulk to "planar" FD-DOI is the less complicated of all transitions so far... that has been one strong point of STMicro on the marketing front. Planar "bulk" and "FD-SOI" share the same BEOF(back end of line) steps ... and some middle to...
But i think it was already revealed (don't remember where but i read it) in an exclusive interview with AMD that Kaveri will debut on "bulk" process. If its low power low clock, mobile parts, as Richland also launched mobile first, is not a bad bet.
EDIT:
50% better at Vdd= 1 volt and 200% at 0.6v.. kaveri could gain much more than 60% perf/power, clearly ahead of intel, cherry on top of cake to "knock your socks off", "forward back gate biasing" was able to get 40% more clock than without it ... simple (it is a relative simple process) is beautiful lol
http://www.advancedsubstratenews.com/2013/06/fully-depleted-soi-and-more-at-vlsi-kyoto-some-knock-your-socks-off-papers-2/
(just read the head lines of those VLSI (kyoto) conference presentations)
And they will catch intel at 14nm, they even plan to reach there first (finfet is quite harder to push and do right)... a bold plan by any metric...
http://www.advancedsubstratenews.com/2013/06/which-will-hit-the-14nm-jackpot-first-fd-soi-or-finfet-gauntlet-down-race-on-2/