AMD CPU speculation... and expert conjecture

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hcl123

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No, who is obsolete is Cray lol ...with a deal to sell all their interconnects to intel (yes they sold out to intel), is highly suspicious that the decision to ditch AMD, the least it has to do is with HTT...

You seem not to understand... HTT is for processor to processor, or in the case of MPUs or APUs for "core" to "core", including here CPU cores to GPU cores... its not exactly for expansion, tough it could be used for expansion, even "device" boards with HTX slots, which don't even have to be cache coherent.

PCIe is strictly now for Expansion, for device boards... not even intel uses it for this for processor to processor... for CPUs they have QPI, which is clearly inferior to HTT, and for kind of APUs (CPU+GPU) they invented a new kind of ring-bus for the purpose, which could never go for "expansion boards"... got it ?

With such obvious advantages tell me how and why is it obsolete ?

Every CPU and APU of AMD (even XBone, PS4) gets HHT tech for the Xbar... though they never mention it that way, but clearly seen in the CPUs that have those links for other sockets directly from the Xbar (no other controller), and when cache coherency is required between CPU and an "accelerator" (AFAIK AMD has no other interconnect tech that can provide CC ) ... and will continue on Warsaw that is compatible with Open Server 3.0... Berlin will be the same of every other APU, and Seattle most probably will have its own ARM interconnects with the addition of PCIe for Freedom Fabric.

Also IOMMU is based of some internals of HTT... though they will never mention that way.

The least that counts is the FSB (front side bus)... this could be PCIe or any other interconnect (matter of fact Intel is more base on QPI than PCIe, though is neither... and this was the way they killed nvidia chipset business), yet the internal Xbar be HTT based, and have links for other processors... integrated or discrete... also HTT( or as i pointed based on a patent, combo HTT+PCIe, which could be integrated, MCM or slotted, specially the HTT part).

 


fanboy linear mathematics is always suspect. if you see perf. numbers from non existent products it's always f.l.m. regardless of brand.
when the pcper editorial was first posted in this thread (yeah, juan's behind times, actually) i said that the writer's claim about HT and jim keller's return to amd do not make sense. unless he's so awesome that within mere months, he made yet another futureproof interconnect that makes HT look obsolete. somehow i doubt that.
Hypertransport is obsolete and one of the reasons that Cray abandoned AMD. Cray is now using PCIe Gen 3 in its new HPC clusters. I have checked and there is no mention to Hypertransport in the HSA spec. Moreover, the substitute of the Opteron (the new Berlin and Seattle) come without Hypertransport. I don't know if Warsaw comes with Hypertransport, but if it comes, this is for legacy users.

Even AMD is using PCIe 3 in its FirePro series for the professional market.

Everything APU is the future for servers, precisely by the same reason that you mention: GFLOP. AMD has already showed some typical server workload where an APU is about 8x faster than a CPU. No strange that Nvidia is preparing its own APU for servers as well.

AMD is not abandoning anything in servers.[/quotemsg]

No, who is obsolete is Cray lol ...with a deal to sell all their interconnects to intel (yes they sold out to intel), is highly suspicious that the decision to ditch AMD, the least it has to do is with HTT...

You seem not to understand... HTT is for processor to processor, or in the case of MPUs or APUs for "core" to "core", including here CPU cores to GPU cores... its not exactly for expansion, tough it could be used for expansion, even "device" boards with HTX slots, which don't even have to be cache coherent.

PCIe is strictly now for Expansion, for device boards... not even intel uses it for this for processor to processor... for CPUs they have QPI, which is clearly inferior to HTT, and for kind of APUs (CPU+GPU) they invented a new kind of ring-bus for the purpose, which could never go for "expansion boards"... got it ?

With such obvious advantages tell me how and why is it obsolete ?

Every CPU and APU of AMD (even XBone, PS4) gets HHT tech for the Xbar... though they never mention it that way, but clearly seen in the CPUs that have those links for other sockets directly from the Xbar (no other controller), and when cache coherency is required between CPU and an "accelerator" (AFAIK AMD has no other interconnect tech that can provide CC ) ... and will continue on Warsaw that is compatible with Open Server 3.0... Berlin will be the same of every other APU, and Seattle most probably will have its own ARM interconnects with the addition of PCIe for Freedom Fabric.

Also IOMMU is based of some internals of HTT... though they will never mention that way.

The least that counts is the FSB (front side bus)... this could be PCIe or any other interconnect (matter of fact Intel is more base on QPI than PCIe, though is neither... and this was the way they killed nvidia chipset business), yet the internal Xbar be HTT based, and have links for other processors... integrated or discrete... also HTT( or as i pointed based on a patent, combo HTT+PCIe, which could be integrated, MCM or slotted, specially the HTT part).
[/quotemsg]
if HT is for core-to-core communication, where does cache stand in the hierarchy? i remember in the console slides that the cpu core and l2 cache were left unchanged while the inter-module communication was being done through the crossbar.
iirc amd's dual gpu cards use some kind of pcie lane multiplexer chip thingie that i never understood how it works (upstream-downstream something). if they went exclusively with HT, won't it break compatibility with pcie specs or create some kind of problem? amd woulda gone HT way by now if ht was so feasible (i am not arguing if it's possible). i doubt that amd's upcoming dual gpu card will use ht links.
edit: could it be that amd's aib partners are reluctant to use ht? validation issues?
 

juanrga

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Another evasive... To be sincere I didn't expect everyone here to accept the real-world example of the FirePro, because it contradicts the 'logic' of some posters here.



You don't read. Do you? If you read posts above yours, you can see myself saying how the old Hypertransport-based processor-processor interconnect has been replaced by the new Ares processor-processor interconnect. I even attached an image with a diagram.

Therefore it is funny that you say me now that Hypertransport connects processors... The new Cray Aries interconnect substitutes the HyperTransport links (used in the old Gemini interconnect) with PCI Express lanes. In fact one of reasons for this substitution was performance and scalability (as Cray admits), but another reason was the wise desire to open the cluster design to processors from other brands (Cray uses the term "processor-agnostic" for its new Aries interconnect), instead being locked to using only old Opterons from AMD.

Your "Cray is obsolete" is very funny, but your appeal to obscure conspiracy theories is still more funny. Not only Cray explains that the move from AMD was motivated by the PCIe 3 requirement for cluster scalability, but AMD admits that Cray abandoned them by the lack of PCIe 3 support in Opteron.
 

juanrga

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More news:

http://arstechnica.com/gaming/2013/09/gabe-newell-linux-is-the-future-of-gaming-new-hardware-coming-soon/

Who here still believes that future gaming machines will be overclocked dual cores running Windows?
 
First, where did you read the word "exclusively"? I cannot find it in anything that I wrote.

x86 is too complicated an arch to be emulated, so this would force an x86+ARM config, which defeats the purpose of going ARM in the first place (power).

Second, Windows also runs on ARM. Nvidia expects a RT+ARM future.

Windows RT, which has zero compatibility with legacy Windows apps. And those apps are the reason people use Windows.

Third, Windows is a minority OS and Microsoft has shown that no longer drives the PC market. AMD announced that abandon Windows exclusivity, and Intel has announced the same at IDC. I gave the link a pair of posts ago. Intel is joining with Google.

Windows drives the market though market share. Linux hovers around 2-3 percent, OSX at 10. It's the lead development platform for that reason.

That being said, Android and OSX [if unified with iOS, as far as running apps go] has a chance of taking significant share away from Windows. But not Linux.

The FX 4000 line will be discontinued, I can promise you that. It has no reason to exist. For like $10 more you can get 50% more cores. And it actually hurts AMD's plans for HSA adoption, as people who buy FX 4000 series are buying into a platform which doesn't support HSA as opposed to an APU that has HSA. FX 4000 series is directly competing with APUs while FX 4000 series harms AMD's HSA push.

Binning. That's why the 4xxx series exists. That being said, its stuck between APU's, i3's, and the 6xxx series, so AMD needs to do SOMETHING with it.

What the hell are you trying to say? Are you implying that there's also no difference between Intel Dual, Intel Quad and Intel Hex as an i3 is just fine in a single core game?

You do see gains going from i3 to an i5 at the same speed, so its clear that i3's, at current clocks, are very close to being overburdened. It's worth noting though: They remain faster on average then any FX chip under 4GHz.

http://translate.google.com/translate?act=url&depth=1&hl=en&ie=UTF8&prev=_t&rurl=translate.google.com&sl=auto&tl=en&u=http://pclab.pl/art50000-12.html

gry.png


In games, on average, the i3 3245 @ 3.4GHz is 4% faster then the FX-8350 @ 4GHz. That's AMD's problem: For games, i5's do command a price premium, and cheaper i3's offer more performance in *most* titles at a cheaper price. I'd still be REALLY interested in a 4Ghz i3...

You remind me of the people I used to talk to before dual core CPUs existed. I said back then "it'd be so cool to have a dual CPU system" and they all laughed, going "nothing will use both CPUs it's a total waste and it always will be."

And I was here, calling those people out. Even then, games used two heavy threads: The main program thread and the primary render thread. So there was an obvious need for duo cores. Beyond that however, focusing on games, you simply do not get much better scaling, because you have multiple threads touching the same objects in memory. And if two threads touch the same object, they can not run at the same time. THAT'S your bottleneck, and who most games, while using 50+ threads, use all but 2-3 for VERY simple tasks.

Now, if you build a single core CPU system now, you're a joke. Coincidentally, at that very same time, Intel was talking about 10ghz Nehalem Pentium chips (the old Nehalem that got cancelled, not LGA1366) and there was a massive wall of FUD on the internet about how multiple cores was a complete waste and we'd have 10ghz Pentiums soon.

I'm going to say this again: If you could clock to infinite speeds, a fast single core will ALWAYS outperform a CPU with any number of cores at a slower speed. But when you have Duo's and Quad's running at the same speed, the Quad will always be at least as good as the duo. That does NOT imply you will see performance gains, however.

And if you remember correctly, AMD made multiple core CPUs back in the day, and now everyone has a CPU with more than one core. Christ, you have to dig pretty deep to buy a CELLULAR PHONE with a single core.

And DEC and dozens of other companies were making systems with multiple CPU's back in the late 60's. PS: They all abandoned those ideas or went bankrupt.

Seriously, do you think we haven't tried multiple CPU's before? We tried in the late 60's and early 80's. And every single time we ran into the same problem: To make the software multiple thread safe, you had to use so much synchronization that you lost almost all the performance gains of using multiple cores to begin with. Some tasks scaled well, and today, those tasks are computed (or co-computed) on the GPU.

The rule for threading is simple: If you have a block of code that touches the same object in memory, you do not thread. If not, then you do. And if you do a bunch of serial processing on a single object in memory, guess what? You can't thread, as it costs you performance to do so.

I've lived through this so many times already. "TWO CORES IS STUPID", "FOUR CORES IS STUPID", "8 CORES IS STUPID". How many times are we going to go through this before you realize that this is the only way to scale x86 CPUs now and that single thread performance gains are DEAD. You're basically advocating that the past is going to be different this time because of reasons that everyone else said in the past and were wrong about. And you're probably all frothing at this ready to go "BUT IM A GAME DEVELOPER!!!! ZOMG LOOK IM AN AUTHORITY ON THE SUBJECT!!!!"

Single core performance gains are alive an well; see an i3 @ 3.4 beating an 8350 @ 4.

Again: YOU CAN NOT THREAD IF THE THREADS IN QUESTION TOUCH THE SAME OBJECT IN MEMORY. Synchronization kills performance gains, essentially forcing you back into serial processing. The stuff we can thread: Rendering, Physics, etc, we do, by offloading to a processor specially designed to handle those workloads.

Your fallacy is thinking only of the CPU. That hasn't been the case for 20 years. The GPU is where the bulk of the workload is being done, and where most of the workload is being handed off to. Stuff that threads well tends to thread VERY well, thus leading to more efficient processing on the GPU, not the CPU.

I mean really, you whine all day long about how it's IMPOSSIBLE for all this sharing of memory to happen, and look: http://en.wikipedia.org/wiki/Transactional_Synchronization_Extensions

No it hasn't, you simply don't understand the downside to Transactional memory.

Transaction memory works on this premise: I'll do the processing, and if the memory contents I started with haven't been modified, then I know some other thread hasn't gone in and used that data, and thus it is safe to overwrite.

The downside, however, if the memory HAS been overwritten, is huge: You have to disregard the processing you just did, put a traditional locking mechanism in place, and do the processing ALL OVER AGAIN. At minimum, a 100% loss in performance for that code block, more if some other thread ends up getting locked out while you are re-doing a lot of your processing.

So here's my question: Would you go for this if you would constantly be jumping between 45 and 10 FPS in a game when this happens, or would you prefer the constant 35 FPS?

Transaction memory works well when the length of the period where the memory is normally locked is small. In that case, the times you have to re-do processing is insignificant to the gains you get by removing synchronization. In short: The 10% of times you need to re-do processing is less then the performance loss of ensuring you compute the output correctly the first time. Databases are a VERY good example of something which would benefit from Transactional memory. Games are not.

So how about actually understanding the subject matter before commenting on it?
 

8350rocks

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FYI, Cray ditched HT because Intel doesn't use it, and Intel more or less bought them.

Intel's QPI system is inferior to HT, and has been for quite some time, by any measureable metric.

As I stated earlier, HT 3.1 provides more throughput than PCIe 3.0.

Let me ask you a question here that's entirely relevant:

If PCIe 3.0 was superior, in any way, to HT 3.1...and consoles are so strapped for throughput badwidth...why, when the capability existed to do it, did the next gen consoles use HT 3.1 over PCIe 3.0? It could have been done just as easily after all.

Additionally, PCIe 3.0 is superior to QPI. So if you make HPCs, and your new owner doesn't use the best throughput technology available at all, though they use the second best throughput technology available well...what are you going to use? What they support right? So, THAT is why the switch from HT 3.1 to PCIe 3.0.

HTX (HT eXpansion) has already been made to work with PCIe 3.0 in the same slot architecture. AMD owns the patent...coincidence? I think not...by the time PCIe 4.0 comes around, we will likely be looking at HT 4.2 or something which is even more throughput by then...you're talking potentially 100+ GB/s throughput through the interconnect system...which PCIe could only ever dream about at this stage.

Also, one final point, IBM could use any throughput system they wanted easily. They are not tied to a specific process at all; however, in their POWER8 systems they *still* use HT 3.1 for throughput because it's the *best* system for it. In fact, IBM has contributed some of the advancements that got us to HT 3.1. Additionally, when using large cluster formations in POWER8 servers, HTX enables you to essentially lose no throughput with multiple CPUs in your system. Which is amazing by any stretch...the *only* system that is out there that rivals/exceeds HT 3.1 is AMD's proprietary Freedom Fabric, that was acquired from purchasing SeaMicro.

Don't you think Cray could benefit from Freedom Fabric, since it's even better than HT for what it does? Though they do not use it...why? Because Intel doesn't have it, and won't pay royalties to use it. In all fairness though, HT is FAR more versatile than Freedom Fabric, though when you're using Freedom Fabric for it's intended purpose...it's very tough to beat.

 

hcl123

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I don't read you say... but you don't understand no matter how many times one posts... you should not read, at least it would save a lot of time lol

No matter how old HTT is, its still *BETTER*... a work of genius of Jim keller among others, and this is *visible* because AFAIK its the ONLY interconnect tech that doesn't require a SERDES mechanism (serializer deserilizer) ... that is one clear feature that makes it superior, ahead of its time no matter how old it is.

But this causes problems to... matter of fact all those **NETWORK fabric interconnects**, cause many other interconnects it must work with are based on SERDES like Ethernet (much included here Freedom Fabric of AMD also-> bought from Seamicro), a SERDES mechanism is better for compatibility, makes it simpler to implement and arbitrate, and when we talk supercomputer fabric interconnects we are already talking something that is overly complicated.

So Cray hasn't replaced HTT, simply because the simple form of HTT was never meant for this **expansion** oriented fabric interconnects, and simply those fabrics are *NOT* PCIe, are proprietary, only route PCIe to entries and exits (so to speak)... and since AMD is the only real implementer of HTT in CPUs, a tight integration of fabric with superior HTT interconnect would make it virtually only for AMD chips( no ARM or Intel or IBM etc.. a real reason why Freedom Fabric is also based on PCIe), and since latency is not really an issue when you have thousands of nodes spread for hundreds of cabinets, then PCIe can work, not the best but can work.

If you want something LIGHT YEARS AHEAD OF CRAY in every aspect *except* real high number of nodes scalability (up to ~8900 nodes) , just take a look at Hypertransport Hypershare, another remarkable ingenious piece of tech based on AMD Hypertransport HNC (high node count) among others (does Ethernet and Infiniband and PCIe *over* Hypershare )

http://www.hypertransport.org/default.cfm?page=Search&cx=003141273436733505860%3Aa8k6mrnat80&cof=FORID%3A11&sa=Search&q=hypershare&sa.x=31&sa.y=11&siteurl=www.hypertransport.org%2Fdefault.cfm%3Fpage%3DProductsViewProduct%26ProductID%3D104&ref=www.hypertransport.org%2F&ss=2044j563238j10

Example of a Hypershare NIC
http://www.hypertransport.org/default.cfm?page=ProductsViewProduct&ProductID=104

Go ahead, read most of those links, instead of accusing others of the guilt.

So Opteron was and will be based on HTT, Cray interconnects were and are based on PCIe... as is AMD Freedom Fabric... too bad and too lame excuses, which doesn't mean HTT is obsolete, the contrary is ahead of its time (and Hypershare even more), to placate a lider that always had clear INFERIOR interconnects, and when a overall reaching interconnect is established (and PCI the base of PCIe is much older and clear obsolete) makes everything less expensive for "compatibility", certification and adoption... and this last are the real reasons... *money*... easier to implement, cheaper, not pursuit of superior techs.

Not only the simple form of HTT is not obsolete, HTT consortium came out recently with a clear superior tech for small to middle/high ground clusters... they are not dead, they are pretty much alive ( never tell this to intel fanboys lol).

 

juanrga

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x86 will be supported for legacy reasons. That is why AMD has released its first ARM server and why AMD claims that ARM "will win", but at the same time AMD is releasing the Warsaw (x86) servers for those customers who are not going to switch to ARM the next year.

The goal of Windows RT is not to run legacy x86 apps, but the new apps.

In the past Windows did drive the market though market share, but this is no longer true. That 2-3% that you quote refers to gaming for desktop/laptop Linux. It doesn't refer to professional uses of Linux, neither to overall market share. Currently Linux/Android overall share is very superior to Windows overall share.

Not only linux/android is already ahead of windows overall share, but it will take on the gaming industry as well. Read the above link with recent Steam presentation and how game developers are abandoning windows for linux.




Are you suggesting that when Cray officially claimed that abandoned AMD because they wanted PCIe 3 support, and when AMD confirmed that Cray move out because of the lack of PCIe 3 support on the Opterons both companies lied. Is that what pretend to say or I am missing something?

Why do you mention QPI? Cray substituted Hypertransport by PCIe 3, in their new Aries interconnect, which is processor agnostic (no locked to Intel QPI).

What part of Cray abandoned Hypertransport because it doesn't scale well I didn't make clear enough? Maybe a quote can clarify things:

For its future Cascade supers, Cray is cooking up a much higher bandwidth interconnect called Aries, which will plug into processors through PCI-Express 3.0 links (this being useful for any processor that supports it) instead of being restricted to Advanced Micro Devices' HyperTransport links.

Consoles are not made of hundred of clusters connected together up to the petascale level, therefore the scaling issue doesn't matter. Moreover, consoles are proprietary custom designs, whereas Cray has designed a cluster/interconnect which is, I repeat again, processor agnostic.

About IBM. Are you aware they are also moving to PCIe 3?

Another surprise in Power8 is IBM's move to the industry standard PCI-Express 3.0 protocol, which the company admitted was much faster than its proprietary interconnect used in Power7 and Power 7+ servers. Oracle has also moved over to the PCI-Express 3.0 protocol with the Sparc M6, which was also detailed at the Hot Chips show.

And IBM proprietary interconnect mentioned therein was everything except slow:

Neither would POWER7's proprietary multipath 360GBps (yes, GigaBytes not gigabits) connections to neighbouring CPUs, up to 32 of them, fit into the nearly 4 times slower 4-channel HyperTransport 3 setup on the AMD G34 socket. The Nehalem-EX 4-channel QPI interconnect, if running at 6.4GTps, would give you above 100GBps bandwidth to the other 4 neigbouring CPUs - yes, also three times slower than the POWER7, but still far from slow in reality.

I know some of you are very enthusiasts about HTX slot GPUs coming soon, but guess what? Read the next quote:

On the investor call where AMD officially announced its plans to acquire ATI, a common theme discussed was AMD's Torrenza strategy. As AMD announced at its analyst day back in June, AMD plans on openly licensing its coherent HyperTransport bus allowing for companies like ATI or NVIDIA to develop GPUs and other co-processors that would plug into a Hyper Transport slot on a motherboard. The benefit is a very low latency, cache coherent interface between the CPU and any other device that it needs to feed large amounts of data to. With ATI operating under AMD's wing, AMD effectively guarantees that we'll see GPUs take advantage of Torrenza.

That was in 2006. Today is 2013 and we are still waiting for the HTX GPU thing, but it is not coming, because Hypertransport is obsolete now. In fact, AMD is phasing out Hypertransport by the new Freedom Fabric.
 

hcl123

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No HTT provides basically the same bandwidth of PCIe v3, and has done so for quite some time, meaning it was ahead of its time (still is) since long.

And in consoles and the like, its not HTT "over" PCIe... its HTT internally, only the fact that HTT has no SERDES makes it quite easier to translate its packets to PCIe, for this last controllers.

AFAIK none form of PCI or PICe has ever routed HTT, it simply lacks "priority interleaving" of packets, a form of "pre-fetch" that is integral with HTT protocol.

OTOH HTT has always routed PCI and PCIe (and several others)... AHEAD OF ITS TIME... but the version HT 3.1, only routes PCIe v2 not v3, the reason why AMD chipsets only have officially support for PCIe v2 graphic boards, having in some board manufacturers, a translating mechanism for this new form of PCIe that has a new *multiplexer* protocol.

So for "COMPATIBILITY REASONS"... and that has been always the case of other interconnects not sanctioned by intel... HTT should be upgraded to be compatible with PCIe v3. Not that is obsolete as it is now, but for compatibilty... and if AMD is smart it should make it 16GT/s, the same speed of PCIe v3, and 2.5x more bandwidth proper for GPGPU, because if AMD doesn't do it, Intel will end making with its superior capacity for releasing new incompatible standards, AMD and other be behind in adoption, and with it be able to lock-in the market...

Everybody is in lala land counting PCIe will always be there, but all of a sudden intel can do QPI 2 with slots and cables and force hard for a transition, making everybody incompatible over night, and grab all the market, without anyone being able to counter-act (JUST ASK NVIDIA)... *STUPIDS* IMHO !..

 

8350rocks

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They could have done a PCIe 3.0 setup similar to others if they wanted to for the consoles...but HT is *that good* that they didn't have to...

Compatibility is the *only* issue there, and AMD could easily rectify that. I think that they would be somewhat foolish to *not* go ahead and upgrade HT to be PCIe 3.0 compatible.

@juanrga:

I brought up QPI because Cray could have used it, but didn't. PCIe 3.0 is only a useful setup for Intel type systems, as HT *already* provides that much throughput. However, Intel doesn't do anything that interfaces with HT and so it would require a completely new hardware solution from the ground up costing lots of money and time resources.

Additionally, if IBM are going to PCIe 3.0 it's the first I've heard of it. They were using a HT based fabric in their large server clusters...and it's capable of 51.2 GB/s of throughput bandwidth...you'd have to look long and hard at another solution to yield that much and do some heavy tweaking. The *only* reason anyone would look at PCIe 3.0 over HT would be simply to take advantage of PCIe 3.0 GPGPUs; though, I cannot make a case for that at this point in time, as most GPGPUs cannot currently entirely saturate PCIe 2.0 x16 (note: I said most, as there may be one out there that can, even if I haven't heard of it).
 

juanrga

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I already announced before how Intel is following AMD strategy of breaking exclusivity with Windows and focusing in linux.

Now Intel has announced that Broadwell doesn't come to desktop, only to mobile/tablets...

http://www.fudzilla.com/home/item/32524-broadwell-won%E2%80%99t-make-it-to-desktop

which matches with AMD strategy of focusing on APUs

Here confirmation of AMD plans for the next gen of Hawai GPUs

http://www.fudzilla.com/home/item/32530-amd-talks-up-hawaii

Again agrees with my view AMD will be not releasing ultra-high cards for a 0.05% of the market. As a consequence, the arguments that I was said, about AMD needing an ultra super-high mega-powerful new CPU to match those future GPUs seems to vanish in the air.
 

hcl123

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Where is the lie ??

To ease expenses with new evolution of their interconnects, and since Cray was and STILL IS in cash straps... they demanded hard for PCIe FSB (front side bus) which AMD didn't had... meanwhile they had already a purposal from intel to buy all their interconnect techs, yet remain able at the same time to use those techs and evolved them (a sweat sweat deal)... i think Cray wouldn't had waited for Opteron with PCIe even if AMD promised a Vishera with it for very soon... (a typical Intel market curbing maneuver, waste lots of money if it serves to cripple competition)

And *notice* the clumsy of this "switch"... which is very tell tell... in the image you provide with Xeon CPUs, the Cray interconnect concentrator and controller, doesn't use the Xeon front bus (FSB), but the "expansion" PCIe links, so this Cray interconnect doesn't function as a *chipset HUB* ... but a network expansion... meaning in a AMD solution those Cray interconnects could connect to a chipset hub ASIC instead of directly to the CPU chips ( price will be identical since same number of chips, performance hardly noticeable) (edt)... which in the immediate makes all your assumptions incorrect. (where in the hell is the "superior" tech ? ... network expansion ? baaaaah! )

 

Cazalan

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All this Cray talk is ancient history now. Time to focus on Seamicro if anything.

BTW, Freedom Fabric isn't a high bandwidth replacement for HT. It's primarily an I/O virtualization technique over PCIe which saves a lot of power.

"SeaMicros interconnect is just PCIe, and the older Atom based cards would support six Atoms from four ASICs. That means PCIe 2x is the maximum each ASIC can see. The big chip version of the ASIC called Freedom supports 2x PCIe2 lanes or 10Gbps. That is about the maximum you will get out of this interconnect, a number that is dwarfed by any modern chip to chip interconnect by an order of magnitude."

http://semiaccurate.com/2012/03/01/why-purchasing-seamicro-was-important-for-amd/

 

hcl123

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?...

In the plans there is a 290x... which arguably everybody agrees is the X2 version, that is, with 2 GPU chips. So after all there seems to be cards for 0.5% of the market lol

My rant with "Hypertransport" and GP/GPUs, is that 290x could/should be a X4 version if HTT is upgraded to PCIe v3 compatibility and 16GT/s ( 128GB/s for a 32bit link which a GPU could have (or 64 bit) ), and no need for PLX like hubs of any kind, direct chip to chip, making the solution cheaper and less power hungry (edt)... and the replacement for Tahiti should be a X2 version in MCM (multi chip module)... and with all this meaning almost half the market...

For one thing, all those individual GPU chips could be much smaller for the same power and performance (matter of fact performance could be quite higher, since the DRAM bandwidth will be cumulative with cache coherency for any GPU chip on multi HTT config, making it proper for hUMA/HSA... a titan to titanic transformer)... yields would skyrocket, and prices could be considerably lower...


 

hcl123

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AFAIK and in the PCIe specs papers, there isn't any mention of FF protocol routing... so is the opposite, its PCIe over FF, its the FF that routes simple PCIe packets not the other way around, facilitated by the fact the FF is based on PCIe for the physical link layers. Yet though the physical connections are basically the same, FF is not PCIe, its a different more elaborated protocol that contrary to the standard PCIe can indeed route also HTT (it is PCIe and HTT over FF (and more as ARM), clear as water since there is Seamicro with BD Opterons).

PCIe is preferred since at the physical layer is basically the same... FF is the protocol that PCIe should had have since long, even in here AMD is ahead lol.. FF is a different distinct interconnect on its own merit.

 

blackkstar

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The reason why people don't see AMD going APU + dGPU is that there's too much power to fit into a socket. BF4 recommends AMD 3m/6c CPU. If AMD goes APU only with maximum of 2m/4c, then they won't even have a suitable gaming chip for games like BF4.

As for your graph, GamerK, we've been over this. There are parts of the game which don't scale well to more cores and there are parts that scale fine. When I was play FC3, there were times when I'd have one core on my FX at 100% usage and the others doing nothing, getting horrible FPS. Other times I'd be getting 90fps and all cores loaded.

You can cherry pick benchmarks to make your point regarding multiple cores benefiting or not benefiting with the current crop of "multi-threaded" games. However even if you show up here and post benchmarks of areas that don't scale to multiple cores, it doesn't change the fact that there are parts of the game where a CPU with many cores will do much better than a CPU with 2 physical cores and HT.

I can just as easily find a graph that shows more cores do scale.

http://i.imgur.com/jjlzCDB.jpg

Like that one.

However the point you're trying to make is invalid. You're trying to make the point that because there are situations where more cores doesn't help, that more cores are useless. Sad to say that there are times when more cores are useless, but there are times when more cores helps. The point I'm trying to make is that more cores CAN help but doesn't always help.

Your argument is

Look at these benchmarks that show my point that I've hunted over the internet for that isn't even a mainstream source because I can't find evidence from a mainstream source that shows what I want to show

You can clearly see that in this specific example, more cores doesn't help

Therefore, more cores never matter at all.

It makes no sense and it's a poor argument. In the graph I provided, FX 8350 was almost 50% faster than core i3 and the Intel hex cores are dominating the top of the charts. You're basically saying that you've provided evidence that i3 and FX 8350 are close and because they're close in your specific situation, FX will NEVER scale well to other games due to its many cores.

I realize you're really passionate about this but you need to step back and try and make better arguments. You're making a fool of yourself by trying to imply that more cores beyond 2 never matters for gaming, ever, and then moving the goal posts and trying to throw out some sort of troll bait by saying i3 beats FX 8350 in your example.

I mean it's cute you thought I was getting mad and that you could troll me, but the jokes kind of on you because everything is going as expected. I knew I just had to get you to open your mouth a little bit to try and make a point to prove you wrong :)
 

juanrga

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As I already said Cray did look for a processor agnostic interconnect. This is the reason why are not using Intel QPI.

If IBM was using a "51.2 GB/s of throughput bandwidth" HT interconnect then the switch to PCIe 3 (96 GB/s of throughput) makes sense. In fact the numbers coincide with what IBM said at hot chips. IBM claimed that the new interconnect in the Power8 offers 2x the bandwidth of the interconnects used in Power7 and Power7+

Not only IBM is going PCIe 3 with the new Power8, but Oracle, Cray, AMD... as well
 

hcl123

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An exaggeration... but yes, for graphics 32 MB of ESRAM can hardly compensate 8 GB of GDDR5 in any metric, but it could be quite better for "compute".

Yet it seems clear Xbone has faster alus... 835 vs 800Mhz... only less, but more elaborated ROP to work with ESRAM and DDR3. PS4 is more "brute" force.

The CPU cores should be pretty the same for all, but in game console this is NOT the determinant factor (the why they choose Jaguar).

 

juanrga

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Besides missing the percentage by one order of magnitude, you are ignoring what AMD claims in the link:

"So this next-generation line is targeting more of the enthusiast market versus the ultra-enthusiast one.”

Basically this means AMD is taking a more frugal approach, as it will not focus on the ultra-high-end market
 

juanrga

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Wait a moment, because BF4 recommends a six core Piledriver CPU. As I have 'shown' in my article about Kaveri, the four core Steamroller APU is essentially at the i5 / FX-6000 level of performance.

Moreover, BF4 is not still next gen. Next gen will offload the heavy computations to the GPU, which implies that CPU will perform still better for the remaining tasks: logic, gameplay...

Whereas I agree with most of the pcper article, I find highly unlikely that AMD will release a six core APU by the end of 2014.
 

noob2222

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Broadwell was never destined to be a DT part. Its going to be hot as fk trying to get to 3.5 ghz. Your being fed marketing BS to make up for the fact that 14nm is extremely dense and too much to keep cool. Shrinking from here on out will only be focused on mobile parts. This is why Intel wants to kill DT systems all together, so they can justify shrinking to 5nm ... lol.

as for your hawaii bs, 30% smaller die size doesn't equate to 30% slower. Obviously you didn't even read the link you provided.

The Hawaii die should end up 10 to 15 percent bigger than Tahiti, yet AMD reckons it can take on much bigger GK110 products

pretty much sais it all right there. 30% smaller, just as fast. The more you talk, the more you prove your eating up this marketing.

Why don't they need an "ultra high end gpu"? because it already is.

Most people who want dual gpu power opt for 2x 7970 instead of one 7990 unless they bought a cheap pos mb that only has one pci-e slot.

The only point of the dual gpu card was for bragging about a single card solution.
 
I committed a sin and got Intel stuff, got Battlefield microstutters, *scratches head* when I made this cash strapping investment it was made on the premise of how awesome Intel is supposed to be, I personally think as always, its a load of hot air and if you are not providing me random synthetics in the real world there actually is very little to tell between a 4770Krap and a APU. Anyways I am a little perplexed and disappointed, it may just be the shame of actually supporting what I universally detest or the fact that I burned a huge hole in the wallet.


PS: saw a lot of bitching on the Memory bandwidth article, why is there no HD5000's, well how is HD4000 and old intel craphics which have shown no scaling going to change with HD5000......*straws clutch grab em now*
 

juanrga

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Except Charlie is wrong.

The SeaMicro Freedom Fabric interconnect included in AMD new Seattle chip is "high-performance" and provides up to 160GB/s.

The Freedom Fabric bandwidth is far above the best than both PCIe Gen 3 and Hyperthreading can offer us. For the sake of comparison the fastest Hyperthreading version tops to about 50GB/s.
 
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