juanrga :
hcl123 :
juanrga :
Interesting reading, seems to confirm everything that I have said in this thread:
http://www.pcper.com/reviews/Editorial/AMDs-Processor-Shift-Future-Really-Fusion/Future-Still-Fusion
No Steamroller for AM3+, only legacy support for 8000/9000 series.
AMD will continue selling 8000/9000 series before releasing top high-performance APUs. No 4M APU for 2014, 3M APU still possible in late 2014 (but unlikely).
Warsaw will be substituted by Excavator version of Berlin.
HyperTransport obsolete.
2/4 cores for mainstream desktop/laptop. 6/8 cores for enthusiast desktops. 4/8/12/16 cores for servers.
Full transition to APUs by about 2015.
Some more predictions/thoughts that the article doesn't consider:
ARM APU for 2016
Move to ARM (from x86) for 2018-2020.
http://www.pcper.com/reviews/Editorial/AMDs-Processor-Shift-Future-Really-Fusion/Future-Still-Fusion
No Steamroller for AM3+, only legacy support for 8000/9000 series.
AMD will continue selling 8000/9000 series before releasing top high-performance APUs. No 4M APU for 2014, 3M APU still possible in late 2014 (but unlikely).
Warsaw will be substituted by Excavator version of Berlin.
HyperTransport obsolete.
2/4 cores for mainstream desktop/laptop. 6/8 cores for enthusiast desktops. 4/8/12/16 cores for servers.
Full transition to APUs by about 2015.
Some more predictions/thoughts that the article doesn't consider:
ARM APU for 2016
Move to ARM (from x86) for 2018-2020.
Very old news with the same old (probably wrong) assumptions. "ITS WHAT EVERYBODY IS SAYING"
* NO more new uarch AM3+ upgrades is pretty clear, since even Warsaw will have a **NEW COMPATIBLE** socket (old G34 is EOL to)... and Warsaw is still PD.
* Hypertransport is not obsolete, even if all adapters will be PCIe, every CPU and APU since this far is a Hypertransport switch for the "internal" Xbar, and HSA IOMMU standard is based on HTT internals. Matter of fact Piledriver was supposed to debut this Xbar/HTT at 4Ghz version with better power management (AND HTT HAS MUCH BETTER POWER MANAGEMENT POSSIBILITIES THAN CRAP PCIe), which seems didn't happen. Perhaps new version of PD Warsaw, and PD FX can have it, even for AM3+, only this will make an upgrade worthed.
Hypertransport perhaps makes the same or more sense in GPGPUS than in CPUs... a MCM of GPUs is what is needed to crush Nvidia definitely without redemption and their monster chip approaches, it would be better in all aspects, and it will be single "chip", single socket SKUs. In this light i'm still hoping for a HTX+PCIe combo slots, though that probably end of 2014 or 2015.
* Everything APU, as in a chip with a GPU is simply NOT the best option for server... server needs GFLOPS not graphics... so a "middle" ground must be found. Else is the same of AMD abandoning server altogether... a very strange and penalizing move, considering that there is an Open Platform definition for server.
Hypertransport is obsolete and one of the reasons that Cray abandoned AMD. Cray is now using PCIe Gen 3 in its new HPC clusters. I have checked and there is no mention to Hypertransport in the HSA spec. Moreover, the substitute of the Opteron (the new Berlin and Seattle) come without Hypertransport. I don't know if Warsaw comes with Hypertransport, but if it comes, this is for legacy users.
Even AMD is using PCIe 3 in its FirePro series for the professional market.
Everything APU is the future for servers, precisely by the same reason that you mention: GFLOP. AMD has already showed some typical server workload where an APU is about 8x faster than a CPU. No strange that Nvidia is preparing its own APU for servers as well.
AMD is not abandoning anything in servers.
No, who is obsolete is Cray lol ...with a deal to sell all their interconnects to intel (yes they sold out to intel), is highly suspicious that the decision to ditch AMD, the least it has to do is with HTT...
You seem not to understand... HTT is for processor to processor, or in the case of MPUs or APUs for "core" to "core", including here CPU cores to GPU cores... its not exactly for expansion, tough it could be used for expansion, even "device" boards with HTX slots, which don't even have to be cache coherent.
PCIe is strictly now for Expansion, for device boards... not even intel uses it for this for processor to processor... for CPUs they have QPI, which is clearly inferior to HTT, and for kind of APUs (CPU+GPU) they invented a new kind of ring-bus for the purpose, which could never go for "expansion boards"... got it ?
With such obvious advantages tell me how and why is it obsolete ?
Every CPU and APU of AMD (even XBone, PS4) gets HHT tech for the Xbar... though they never mention it that way, but clearly seen in the CPUs that have those links for other sockets directly from the Xbar (no other controller), and when cache coherency is required between CPU and an "accelerator" (AFAIK AMD has no other interconnect tech that can provide CC ) ... and will continue on Warsaw that is compatible with Open Server 3.0... Berlin will be the same of every other APU, and Seattle most probably will have its own ARM interconnects with the addition of PCIe for Freedom Fabric.
Also IOMMU is based of some internals of HTT... though they will never mention that way.
The least that counts is the FSB (front side bus)... this could be PCIe or any other interconnect (matter of fact Intel is more base on QPI than PCIe, though is neither... and this was the way they killed nvidia chipset business), yet the internal Xbar be HTT based, and have links for other processors... integrated or discrete... also HTT( or as i pointed based on a patent, combo HTT+PCIe, which could be integrated, MCM or slotted, specially the HTT part).