juanrga :
i)
They didn't miss 8% of CPU target, because AMD never revealed the frequencies. In my BSN* article I included a table with three different combinations of frequencies. Final Kaveri CPU freq. is only a 3% behind one of them.
The same about the GPU frequencies. AMD never gave them.
ii)
I already explained you that only the GDDR5 version of the HD7750 has 900MHz clocks. The version with DDR3 has 800MHz clocks. Kaveri has 720MHz. All them bulk.
The large drop in iGPU performance from original expectations is explained by AMD dropping the GDDR5 support. The original 1050GFLOP Kaveri was considering GDDR5 memory. BSN* has copies of the original docs reporting GDDR5 support. I already mentioned that someone has said me that the Kaveri die has a disabled GDDR5 IMC. Which means that the decision to abandon GDDR5 was taken very late.
iii)
Trinity and Richland are 100W. Kaveri is limited to 95W TDP. Limit both Trinity and Richland to 95W max and say me about how many you drop frequencies.
My bet is that a 95W rated Trinity would be ~3.7GHz and Richland ~3.9--4.0GHz
iv)
Kaveri has larger and powerful iGPU than Trinity/Richland. Those 100W TDP for the APU are distributed between CPU and GPU.
Take Trinity/Richland and substitute their iGPU with a Kaveri-level iGPU. If the total TDP continue being of 100W, you have to cut the CPU frequencies by some extension.
v)
Sure that Kaveri would achieve higher clocks in SOI. Has someone said the contrary here? NO But are you aware that Glofo has not ready 28nm SOI? AMD decision to go bulk has been a success. I don't understand why you guys don't accept it.
vi)
We don't know turbo frequencies nor its aggressivity. What if AMD follows Intel way of lower base clocks and higher turbo clocks?
The last rumor is that AMD is considering >4.0GHz turbo.
vii)
In my BSN* article I didn't considered a 20% IPC gain over PD, but a 20% minus a 5% for unknows. Palying safety, this means that my predictions of i5 level of performance are off by about a 3%.
Now, benchmarks leaked after I wrote my article say that SR is a 31% faster than PD and speculate about higher gains in the final silicon
It is still too soon. There are so many unknows.
viii)
It is evident than FinFET is the future. AMD is already tapping out chips on 14nm bulk FinFET and some foundries are running the first tests of 10nm FinFET.
But hey you are the expert that said us that Kaveri was SOI...
I. http://semiaccurate.com/2013/11/12/amd-misses-expectations-kaveri/
AMD did announce targets at the financial analysts day in the summer. 4.0 GHz and 900 MHz were the targets...how else did you arrive at your speculated numbers? You pulled them out of the sky? The GFLOPS number they gave was what you used...remember? Selective memory? Alzheimer's?
II. You're dismissing it because you don't want to admit they missed their targeted performance bracket on bulk. It would make your entire argument wrong.
III. That's right, a 95W Richland part would still have higher clocks on a less advanced process. See something wrong with that? Trinity level base clocks (i.e. 1.5 generations ago) are not acceptable.
IV. You're neglecting that Kaveri is also using GCN which is supposed to consume less power than VLIW4, which is what was on Trinity/Richland. Your argument holds no water.
V. Because it is a failure, and behind the scenes, AMD is basically almost admitting as much without outright saying it missed the performance targets because of process constraints. I want AMD to succeed as much, or more, than you do; however, we should be calling a spade what it is, a spade. Kaveri is a great APU, which tends to be a upper low end part in the flagship SKU. Berlin server APUs/CPUs are aimed at lower power/lower compute demand servers. People who need to crunch data go for 16 core Opterons. That's specifically because
they're still better at that than APUs.
VI. That would suit AMD's TC 3.0 setup on Richland, 300 MHz turbo would put TC @ 4.0 GHz, now the issue arises, how often will turbo engage? Most of the time like Intel, or only a small portion of the time like the last gen AMD processors? Even then, it still doesn't mitigate the fact that the 6800k has a turbo of 4.4 GHz.
VII. 3%
on the CPU only calculations. They are off as much as 19% in the CPU + GPU possibility calculations. Additionally, you assumed a 4.0 GHz clock, you've now not only lost an extra 3% clock speed, however, you're also 5% shy of what the improvement actually looks to be so far. Which puts your estimates closer to 8% off. Not trying to be a downer, but reality is where we live, and that has to be accounted for.
VIII. No, AMD is beginning to develop for 14nm XM, which is not a FinFET.
It could be, though you'd have to design a FinFET to go on 14nm XM substrate (14nm FE with 20nm BEOL). 14nm XM could also be FD-SOI...as STMicro already has some designs for booster tech on that technology as well. Consider that 14nm XM was co-developed with STMicro, they are prepared for whatever it needs to be.
I am not sure why GF has such issues with 28nm booster tech for FD-SOI, personally I think it has everything to do with the delays on 28nm bulk, because you cannot implement BEOL booster tech for FD-SOI if you don't have bulk going yet.
Either way, AMD is being hamstrung by GF over the process technologies they have access to...which is why Kaveri is being made at TSMC, not GF. I expect if they get future FD-SOI tech up and running at acceptable levels, we might see FX successor @ GF. Though currently, that doesn't look likely to happen until GF sort out their issues.
FYI: the only foundry currently using a FinFET is Intel's foundry, and their FinFET is on bulk substrate. That's also why they have had yield issues with the last few CPUs and high overclock variance. Because a FinFET is very complex, and doing it on bulk requires additional mask layers to prevent leakage, making even more issues. Though, I hope Intel doesn't see the light...because FinFET is arguably dead before it got off the ground. Maybe when they chase something past 7nm it will take off...(if FinFET can indeed get to 5nm as some have speculated).
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