AMD CPU speculation... and expert conjecture

[de5_Roy]

Is there some sort of way to use multiple dies in a single package? Ergo you make a big GPU and a big CPU and put the two together?

cooling would be a nightmare. it can be done as both cpu and gpu soldered to the motherboard a la laptop motherboard. but i think you're asking for something like an m.c.m. packaging.

i think that the mid section would be excessively hot and cause chip-to-chip interconnects to melt.

 

[gamerk316]

Is there some sort of way to use multiple dies in a single package? Ergo you make a big GPU and a big CPU and put the two together?

Yields start becoming a problem then, making it economically a non-starter.

I do not think a 90% GPU APU would be very good. AMD's own documentation states that both CPU and GPU are required for HSA to work. 90% GPU APU is throwing out almost all latency computer for throughput.

Not everything will be HSA. As I have said in the past, something like a 90% GPU APU would leave you with something that absolutely sucked at traditional CPU tasks. And no matter what you do, you're going to have legacy software.

AMD seems to be banking on all software becoming massively parallel, which I've said from day 1 will not be happening.

 

[juanrga]

AMD tweet: "Something SMALL is coming and it’s BIG news! Can you guess what it is? Click for a hint!"

Mobile Kaveri I guess

Considering how parts of the CPU are not "bright" I would say it is some UMD CPU. Maybe it has the ability to turn off certain parts like Intels Atom does when it is not used and that is why certain parts are dim?

The page started with only a small part of the image bright and rest in black. with countdown each day some new part of the die is revealed (bright). Today almost all the die is visible.

 

[colinp]

It looks identicle to Kabini. I can't see any significant difference any way.

http://www.cpu-world.com/news_2014/2014042801_AMD_to_launch_Beema_and_or_Mullins_core_on_April_29_.html

 

[8350rocks]

Yaay.

A new chip is coming.

Can't tell you if it'll be 2015, 2016 or beyond.

Can't tell you if it'll be AM3+, FM2+ or something else.

Can't tell you if it'll have L3 and / or integrated graphics.

Can't tell you if it's Excavator, Big Cat or something else.

Can't tell you if it'll be quad, octo or deca core or module.

Can't tell you if it'll use DDR3, DDR4 or something else.

Can't tell you the TDP either.

But hold onto your hats, don't let your socks get blown off, something's coming for sure.

I can give you the most accurate speculation based on what I do know...

Based on current situations I can speculate it will likely be 1H next year...my best guess.

Platform? I have not had confirmation that AM4 is not coming (I have asked)...so, from what I am hearing my best guess is either FM2+ or AM4. They are waiting for DDR4 to come first to offer compatability with it, plus it should be more affordable by that time as well.

We shall see...those are my best rough estimations at this point. AMD is being unusually tight lipped about all this. However, when I go to the CPU HQ in Austin in June I will see what I can find out

 

[juanrga]

The evolution of computing has always been towards integration. Do you know that some years ago the floating point unit was an external coprocessor attached to a special socket?

I second this. Was it here that I did a write up on the trend of integration? We've seen it happen to everything, the controller boards for hard drives... dedicated to on-board audio. Mainstream integration of the GPU is only the next logical step before we see the next component merger which I personally believe will be between memory and storage.

Yes, integrating the GPU is the next logical step as even the Nvidia Research Team agrees:

In this time frame, GPUs will no longer be an external accelerator to a CPU; instead, CPUs and GPUs will be integrated on the same die with a unified memory architecture.

System memory will start to be introduced on package about 2015--2016 and years later it will be stacked on die.

And physics dictates that you'll get less then half the ability of both. Die sized can only get so big and there is a limit to the amount of power you can put into them. Two chips will always have a higher size and power ceiling then a single chip. Above I gave a break down of the performance characteristics of the most powerful APU vs two discrete solutions, especially the external GPU. Also juan was horribly incorrect in his statement, the Xeon Phi is nothing but a giant array of external SIMD FPUs. The same thing with the NVidia and AMD dGPU's, they are just giant external vector coprocessors. The internal FPU's on both the Intel and AMD CPU's are perfectly fine at running the code required to render 3D images, that was the entire purpose behind MMX, 3DNOW and SSE. External solutions are so much faster they make the SIMD FPU look like a slide show in comparison.

Sorry, but I already showed that physics says otherwise. You are making some elementary mistakes, which were corrected before.

I also gave you a quote from Nvidia Research Team showing that they openly disagree with you and agree with me.

I also gave you an official slide from Intel claiming just the contrary for the Xeon Phi. Intel will replace the current discrete PCIe card coprocessor by a future standalone 'CPU' on socket because the last is faster than the PCIe card. I could also give link to Intel CTO claiming how they envise a future where Phi cores and Xeon cores are merged in same die... just as I predicted.

 

[8350rocks]

Is there some sort of way to use multiple dies in a single package? Ergo you make a big GPU and a big CPU and put the two together?

cooling would be a nightmare. it can be done as both cpu and gpu soldered to the motherboard a la laptop motherboard. but i think you're asking for something like an m.c.m. packaging.

i think that the mid section would be excessively hot and cause chip-to-chip interconnects to melt.

Not necessarily...but it would be rather inefficient comparatively in terms of die size and yields versus just doing a dGPU.

 

[juanrga]

I do not think a 90% GPU APU would be very good. AMD's own documentation states that both CPU and GPU are required for HSA to work. 90% GPU APU is throwing out almost all latency computer for throughput.

Not everything will be HSA. As I have said in the past, something like a 90% GPU APU would leave you with something that absolutely sucked at traditional CPU tasks. And no matter what you do, you're going to have legacy software.

The die is large enough and the 10% of it is enough to place 8 CPU cores that are more powerful and fast than Piledriver cores used in the FX/Opteron CPUs.

The AMD doc details that their ultra-high-performance APU concept, includes an iCPU with 256-bit FMAC units, L3 cache, and quad-channel memory controller. This means that assuming 4GHz, the iCPU offers maximum of 512GFLOPS. The FX-9590 CPU peaks at 301GFLOPS

Considering only the peak performance the iCPU is about 70% faster than FX-9590.

And this is not the fastest design that I have seen. The diagram of the 'APU' currently designed by the WG of the Japan SDHPC architecture WG for their national supercomputer plan includes an iCPU rated at 1TFLOPS. The iCPU includes 128MB of LLC.

 

[juanrga]

AMD seems to be banking on all software becoming massively parallel

No. In fact, the HSA architecture is explicitly designed to deal with both serial and parallel software at once.

 

[gamerk316]

AMD seems to be banking on all software becoming massively parallel

No. In fact, the HSA architecture is explicitly designed to deal with both serial and parallel software at once.

I was referring to their core design; HSA has nothing to do with it.

Also, while I have no doubt Intel/AMD/NVIDIA will push high powered APU-like chips that cost $10,000, I can also guarantee, due to yields and physics, they will never be adopted outside of the super-high end supercomputer segment. Its not happening.

 

[juanrga]

AMD releases Mullins and Beema: slides, specifications, and performance here

http://wccftech.com/amd-power-mullins-mainstream-beema-apu-detailed-powered-puma-x86-gcn-cores-launches-tomorrow/

 

[Cazalan]

Is there some sort of way to use multiple dies in a single package? Ergo you make a big GPU and a big CPU and put the two together?

Yes. This is what Xilinx does with their large FPGAs. Using between 4 and 8 die on a silicon interposer.

But they cost 5 - 15 thousand dollars a pop. Not for the general consumer. These make the Titan Z look cheap.

 

[juanrga]

AMD seems to be banking on all software becoming massively parallel

No. In fact, the HSA architecture is explicitly designed to deal with both serial and parallel software at once.

I was referring to their core design; HSA has nothing to do with it.

Also, while I have no doubt Intel/AMD/NVIDIA will push high powered APU-like chips that cost $10,000, I can also guarantee, due to yields and physics, they will never be adopted outside of the super-high end supercomputer segment. Its not happening.

What core design? That from Keller? Are you aware that HSA requires a hardware architecture with both serial and parallel compute units?

Evidently the 300W ultra-high-performance APUs will be focused to workstations, high-end servers, and supercomputers, but this is not different from current Xeons, Opterons, Powers, Teslas, Phis, FirePros... Or do you see lots of home PCs with some 12-core $1000 Opteron paired with a $4800 Nvidia K40? Some tablet?

The APU design that I have in mind scales down from the top supercomputer model to the phone model, providing the best performance possible at each power level.

 

[8350rocks]

AMD seems to be banking on all software becoming massively parallel

No. In fact, the HSA architecture is explicitly designed to deal with both serial and parallel software at once.

I was referring to their core design; HSA has nothing to do with it.

Also, while I have no doubt Intel/AMD/NVIDIA will push high powered APU-like chips that cost $10,000, I can also guarantee, due to yields and physics, they will never be adopted outside of the super-high end supercomputer segment. Its not happening.

What core design? That from Keller? Are you aware that HSA requires a hardware architecture with both serial and parallel compute units?

Evidently the 300W ultra-high-performance APUs will be focused to workstations, high-end servers, and supercomputers, but this is not different from current Xeons, Opterons, Powers, Teslas, Phis, FirePros... Or do you see lots of home PCs with some 12-core $1000 Opteron paired with a $4800 Nvidia K40? Some tablet?

The APU design that I have in mind scales down from the top supercomputer model to the phone model, providing the best performance possible at each power level.

Interestingly enough, AMD has no offices in Spain.

So, now that you have spread your conjecture through here for a while, let us stop discussing things that probably will not come to pass anytime soon, and instead focus on something that is waiting in the wings realistically...

Excavator, and other upcoming (in the near future) products...

That way we can stop screwing about with stuff that is 10-20 years out at best.

 

[vmN]

Excavator will actually be an "performance" improvement, with its improved SIMD with AVX2 support.

I do believe AMD could release a HEDT excavador standalone CPU, hopefully AMD can push another integer pipeline into each ALU cluster, so we a great boost in both integer and SIMD instruction.

I doubt they will make any huge change to their cache system, as long as they are running with the CMT technology.

I also doubt we will see any 8 core APU any time soon from AMD, as they seems to strugle featuring both the iGP and L3 cache.

 

[de5_Roy]

Mullins And Beema APUs: AMD Gets Serious About Tablet SoCs
http://www.tomshardware.com/reviews/amd-tablet-processor,3813.html
they're here!!

A first look at AMD's Mullins mobile APU
And a primer on Beema
http://techreport.com/review/26377/a-first-look-at-amd-mullins-mobile-apu

AMD Beema/Mullins Architecture & Performance Preview
http://www.anandtech.com/show/7974/amd-beema-mullins-architecture-a10-micro-6700t-performance-preview

promo slides on one page...
http://www.fudzilla.com/home/item/34612-amd-launches-beema-boasts-huge-efficiency-improvements


edit: lately, i've been noticing the "another prediction confirmed!" game, here is mine (posted before, rehashing to annoy readers...again) on new low power socs

Spoiler

but i can use tags, so i use spoiler

it's that time of the year again. time to make prediction on upcoming low power amd apus/socs. yay!
for puma, i am predicting:

dual channel lp/ddr3/l 1600/1866 support.
2.5ghz max. clockrate on single core, 2.1-2.2 ghz on all cores.
turbo in both cpu and igpu.
user-configurable tdp like kaveri a8 7600.

for the igpu:

lowest clockrate 300 mhz, max. clockrate 700-850 mhz.
128 gcn 1.1 cores, uvd 3.0 (or whichever is the latest one). i want to see 256 cores. but that'll prolly double the igpu area on the die.
possibly 2-4 a.c.e. at least 2.

let's see which ones turned out right....
ddr3l 1866 support, turbo, 4 ace, 128 shaders, min. 300mhz igpu cockrate all confirmed. i saw 2.2 ghz in one promo slide, so that'd confirmed as well. another max. clcokrate was 2.4, which is within the error margin of 2.5, so it's confirmed. same with max. igpu clockrate of 800 mhz, which is within predicted 850 mhz range, so it is confirmed. so all of my predictions are confirmed. i am so accurate! yay!
i'll let you in on a secret: i never used any technological know-how for those predictions, just padded percentage numbers over kabini specs.

 

[colinp]

Mullins And Beema APUs: AMD Gets Serious About Tablet SoCs
http://www.tomshardware.com/reviews/amd-tablet-processor,3813.html
they're here!!

A first look at AMD's Mullins mobile APU
And a primer on Beema
http://techreport.com/review/26377/a-first-look-at-amd-mullins-mobile-apu

AMD Beema/Mullins Architecture & Performance Preview
http://www.anandtech.com/show/7974/amd-beema-mullins-architecture-a10-micro-6700t-performance-preview

promo slides on one page...
http://www.fudzilla.com/home/item/34612-amd-launches-beema-boasts-huge-efficiency-improvements

Looks promising, now all they need is to deliver some design wins.

Hey, here's a thought. Stick a bunch of that high TDP L3 on there, raise the clocks, add in dual channel memory, beef up the FPU... you know where I'm going with this.

 

[esrever]

I really wish AMD would partner with someone like HP to bring the discovery tablet platform out but I guess they don't have much money to launch something like that and market it.

 

[de5_Roy]

Looks promising, now all they need is to deliver some design wins.

Hey, here's a thought. Stick a bunch of that high TDP L3 on there, raise the clocks, add in dual channel memory, beef up the FPU... you know where I'm going with this.

yeah. especially amd's new power management system. i assume they're testing it out before it carries over to carrizo socs. it could possibly be the secret sauce behind carrizo's targeted 65w tdp range. we'll have to wait for a proper review and power measurement numbers to be certain.

if amd can solve their cache subsystem issues, they might not need L3 cache for ulp socs. in the die shot, you'll notice that the L2 cache area is the 3rd largest area after the igpu and the cpu cores. in area-limited socs, putting on L3 cache isn't feasible. even in the performance apus, the igpu takes the biggest space, then cache and cpu cores. L3 cache won't add much of performance for the die space it would occupy.

 

[colinp]

yeah. especially amd's new power management system. i assume they're testing it out before it carries over to carrizo socs. it could possibly be the secret sauce behind carrizo's targeted 65w tdp range. we'll have to wait for a proper review and power measurement numbers to be certain.

if amd can solve their cache subsystem issues, they might not need L3 cache for ulp socs. in the die shot, you'll notice that the L2 cache area is the 3rd largest area after the igpu and the cpu cores. in area-limited socs, putting on L3 cache isn't feasible. even in the performance apus, the igpu takes the biggest space, then cache and cpu cores. L3 cache won't add much of performance for the die space it would occupy.

The point I was trying to make is that this looks really promising from a performance per watt point of view and so there may be scope to scale this way beyond the tablet form factor.

Remember the last time a big semiconductor company took a mobile architecture and scaled it up to higher TDP envelopes to replace a high frequency, high TDP, under performing chip that had made them the laughing stock of the industry?

 

[juanrga]

Interestingly enough, AMD has no offices in Spain.

So, now that you have spread your conjecture through here for a while, let us stop discussing things that probably will not come to pass anytime soon, and instead focus on something that is waiting in the wings realistically...

Excavator, and other upcoming (in the near future) products...

That way we can stop screwing about with stuff that is 10-20 years out at best.

First, the designs from Intel, AMD, and Nvidia are scheduled for the year 2018. That is only four (4) years out.

Second, I already discussed Excavator here. I was one of the first that predicted it comes only in APU (Carrizo), when people here was still speculating about a new FX CPU from AMD ("wait for the official roadmap" I was said then). I also discussed here max. TDP of Carrizo, fabrication process (it is not SOI ), DDR support, socket support, and leaked the wide of the FMAC units. I also did an estimation of performance of excavator compared to Steamroller. Do you remember the percentage gains?

Moreover, I also said that the successor of Carrizo APU is named Basilisk, which is another... APU. I mentioned a pair of posts ago that AMD is working on bringing stacked ram support for that APU. I also mentioned that Keller is working in a new architecture (post-Excavator) which is scheduled for 2016 and that a new graphics architecture (developed by Koduri) is also scheduled for 2016.

Of course, you can expect some last minute adjustments and maybe delays (Kaveri was initially scheduled as replacement of Trinity), but all of the above is part of the what I discussed here.

Please refresh me, which is your contribution to this thread? Some vague statements of the kind "AMD is going to release something"?

 

[juanrga]

The point I was trying to make is that this looks really promising from a performance per watt point of view and so there may be scope to scale this way beyond the tablet form factor.

Remember the last time a big semiconductor company took a mobile architecture and scaled it up to higher TDP envelopes to replace a high frequency, high TDP, under performing chip that had made them the laughing stock of the industry?

I recall that I mentioned several pages ago my desire about AMD replacing the cat cores by ARM cores (this already happened on server), to kill the big Bulldozer cores (apparently 2015 is the date), and to scale up the cat cores to replace Excavator.

I also gave this relevant link

http://www.extremetech.com/computing/174980-its-time-for-amd-to-take-a-page-from-intel-and-dump-steamroller

 

[juanrga]

An interesting slide about future products:

Even Anand has something good to say about Beema/Mullins:

We finally have AMD silicon, built around a non-Bulldozer architecture, that seem to have turbo capabilities comparable to Intel’s. The result is a completely different performance profile. While AMD’s Jaguar cores in Kabini and Temash were easily outperformed by Intel’s Bay Trail, Puma+ pulls ahead. AMD continues to hold a substantial GPU performance advantage as well.

http://www.anandtech.com/show/7974/amd-beema-mullins-architecture-a10-micro-6700t-performance-preview/4

 

[gamerk316]

^^ So wait, going away from low-IPC cores tends to improve performance? I'm shocked I tell you, shocked!

 

[Embra]

Gigabyte’s AMD-powered mini gaming PC reviewed.

http://arstechnica.com/gadgets/2014/04/fast-but-compromised-gigabytes-amd-powered-mini-gaming-pc-reviewed/