AMD CPUs, SoC Rumors and Speculations Temp. thread 2

[cdrkf]

Ah so it's probably a k12 based part then. if it pans out still a worthwhile win.

 

[juanrga]

Ah so it's probably a k12 based part then. if it pans out still a worthwhile win.

The same rumor says:

It is still a mystery whether the ARM-based system-on-chip is powered by AMD’s own K12 high-performance core due in 2016 or ARM’s off-the-shelf Cortex-A57 or A72 cores. However, keeping in mind that this is going to be a full-custom CPU, expect it to feature special-purpose intellectual property from Facebook (e.g., accelerators, instructions, links, etc.) custom I/O configuration and various other ways to tailor the SoC for Facebook’s workloads.

But considering that K12 has been delayed to 2017, I am about to claim that it is based in ordinary A57 cores.

 

[cdrkf]

Ah so it's probably a k12 based part then. if it pans out still a worthwhile win.

The same rumor says:

It is still a mystery whether the ARM-based system-on-chip is powered by AMD’s own K12 high-performance core due in 2016 or ARM’s off-the-shelf Cortex-A57 or A72 cores. However, keeping in mind that this is going to be a full-custom CPU, expect it to feature special-purpose intellectual property from Facebook (e.g., accelerators, instructions, links, etc.) custom I/O configuration and various other ways to tailor the SoC for Facebook’s workloads.

But considering that K12 has been delayed to 2017, I am about to claim that it is based in ordinary A57 cores.

Possibly, although I guess it depends in what way K12 has been 'delayed'? For example it could be that K12 is pretty much done and could be taped out for next year, however AMD are holding off launching it to the market until the following year due production costs of running multiple designs at the same time. That wouldn't preclude using it in a custom design although I guess whichever way you look at it, it does show some potential in the 'semi-custom' approach beyond game consoles.

 

[gamerk316]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

 

[jimmysmitty]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That will be a HUGE chip. 8M L3 per 4 cores and 16 cores? Cache is one of the largest parts of a CPU (not counting the GPU if it has one .

and that is just 20MB of cache, imagine 32MB of L3 cache.....

Then add in that GPU which could be big.

I hope AMD has something decent or else. Don't want to see another flopper.

 

[esrever]

Fud has been pushing that "leak" for months. I would be surprised if it turned out to be real.

 

[gamerk316]

I hope not; the yields on a chip that large won't be good. Which means the profit per sale won't be good, which won't help AMDs declining financials, regardless of how the chip actually performs. Nevermind TDP could become an issue.

So yeah, this better not actually be Zen, otherwise AMD is done.

 

[jimmysmitty]

It is probably the same is the namesake of that site, FUD. That chips would be much too large. I remember seeing rumored designs for AMDs BD that were multicore with a full GPU on it too.

 

[gamerk316]

Hence why I said "Take it for what it's worth". Then again, I remember when the BD cache latencies were leaked, and EVERYONE, including myself, said "No way they could be THAT bad.". Whoops.

 

[-Fran-]

Can we define a bit better what "big" means?

I ask that because Fiji is also "big". And there, big means "maximum allowed for the process". I don't remember more details, but Fiji is pretty big and GPUs are usually pretty massive; same for the GM210. So, 300mm2? 500mm2? 600mm2?

That information (Fudz'es) might go on several ways in terms of speculation. Well, if you want to believe it in part at least, haha.

My first road is making the CPU 50/40 (not like 30/50) of die space (leaving ~10% for the IMC and other stuff), packing those 32MB of L3 dwarfing everything else, except the GPU. It would be a 125W part or a 65W for Servers? Since they won't need to clock it high (that's the idea of departing from Dozer), even though it's "big" should be around current Xeons in terms of power at least.

Another road is not trusting there are 8MB and it's 4MB or 6MB per 2 cores, giving a more known "proportion" for the CPU size. The GPU will still be massive if they're aiming to do a server APU.

And the 3rd road is the GPU will be minimal and the CPU will use most of the available space. In my mind this would be a 65/25 split.

So, we have to make the connection with available process nodes they will be targeting and just put some numbers around transistor size for cache and assuming the GPU will stay more or less the same (in terms of transistors) against Carrizo's iGPU... I guess.

Cheers!

 

[jimmysmitty]

Big as in larger than anything currently available. If that spec is true it will be larger than Intels i7 5930x which is already big. Cache is pretty big overall so more means bigger die size and also can mean higher TDP.

Again that is if that is true.

 

[juanrga]

Ah so it's probably a k12 based part then. if it pans out still a worthwhile win.

The same rumor says:

It is still a mystery whether the ARM-based system-on-chip is powered by AMD’s own K12 high-performance core due in 2016 or ARM’s off-the-shelf Cortex-A57 or A72 cores. However, keeping in mind that this is going to be a full-custom CPU, expect it to feature special-purpose intellectual property from Facebook (e.g., accelerators, instructions, links, etc.) custom I/O configuration and various other ways to tailor the SoC for Facebook’s workloads.

But considering that K12 has been delayed to 2017, I am about to claim that it is based in ordinary A57 cores.

Possibly, although I guess it depends in what way K12 has been 'delayed'?

It was originally going to be released in 2016. Then delayed to 2017.

 

[juanrga]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That is a diagram for the server APU scheduled for 2017, not the Zen CPU scheduled for 2016.

The information in that link is music to my hears! It pretty much confirms my predictions about Zen, including my former claim that Zen will not support Skylake new ISAs.

I hope not; the yields on a chip that large won't be good. Which means the profit per sale won't be good, which won't help AMDs declining financials, regardless of how the chip actually performs. Nevermind TDP could become an issue.

So yeah, this better not actually be Zen, otherwise AMD is done.

Who said that is a monolithic die design?

 

[juanrga]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That will be a HUGE chip. 8M L3 per 4 cores and 16 cores? Cache is one of the largest parts of a CPU (not counting the GPU if it has one .

and that is just 20MB of cache, imagine 32MB of L3 cache.....

Then add in that GPU which could be big.

I hope AMD has something decent or else. Don't want to see another flopper.

That diagram is showing 20MB shared among 8 Haswell cores. Zen shares 8MB per quad-cluster. Thus 8 cores would share only 16MB, or nearly 3/4 of the cache on that figure.

 

[jimmysmitty]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That will be a HUGE chip. 8M L3 per 4 cores and 16 cores? Cache is one of the largest parts of a CPU (not counting the GPU if it has one .

and that is just 20MB of cache, imagine 32MB of L3 cache.....

Then add in that GPU which could be big.

I hope AMD has something decent or else. Don't want to see another flopper.

That diagram is showing 20MB shared among 8 Haswell cores. Zen shares 8MB per quad-cluster. Thus 8 cores would share only 16MB, or nearly 3/4 of the cache on that figure.

I know that, I was using it as a size comparison. Cache takes up a lot of real estate is what I was getting at so just due to the cache amount (32MB total) it will be a big chip even without the iGPU part.

 

[juanrga]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That will be a HUGE chip. 8M L3 per 4 cores and 16 cores? Cache is one of the largest parts of a CPU (not counting the GPU if it has one .

and that is just 20MB of cache, imagine 32MB of L3 cache.....

Then add in that GPU which could be big.

I hope AMD has something decent or else. Don't want to see another flopper.

That diagram is showing 20MB shared among 8 Haswell cores. Zen shares 8MB per quad-cluster. Thus 8 cores would share only 16MB, or nearly 3/4 of the cache on that figure.

I know that, I was using it as a size comparison. Cache takes up a lot of real estate is what I was getting at so just due to the cache amount (32MB total) it will be a big chip even without the iGPU part.

Yes, the APU has 16 Zen cores, because about half the chip is iGPU, whereas the CPU uses the whole chip for a maximum of 32 Zen cores. But I don't think that is something specially bigger. E.g., Intel is actually selling 18 Haswell cores and 45MB L3 on 22nm.

To me bigger is something like this: 648mm² and comes with 96MB of L3

 

[cdrkf]

http://www.fudzilla.com/news/processors/38456-a-few-more-details-about-amd-s-zen

Can't be the HEDT variant, due to the chip being an APU, right? And as per, take source for what you will.

That will be a HUGE chip. 8M L3 per 4 cores and 16 cores? Cache is one of the largest parts of a CPU (not counting the GPU if it has one .

and that is just 20MB of cache, imagine 32MB of L3 cache.....

Then add in that GPU which could be big.

I hope AMD has something decent or else. Don't want to see another flopper.

That diagram is showing 20MB shared among 8 Haswell cores. Zen shares 8MB per quad-cluster. Thus 8 cores would share only 16MB, or nearly 3/4 of the cache on that figure.

I know that, I was using it as a size comparison. Cache takes up a lot of real estate is what I was getting at so just due to the cache amount (32MB total) it will be a big chip even without the iGPU part.

Yes, the APU has 16 Zen cores, because about half the chip is iGPU, whereas the CPU uses the whole chip for a maximum of 32 Zen cores. But I don't think that is something specially bigger. E.g., Intel is actually selling 18 Haswell cores and 45MB L3 on 22nm.

To me bigger is something like this: 648mm² and comes with 96MB of L3

I agree with you on this, that doesn't look outside the realms for a server part. Also keep in mind that with the new interposer designs as Juanrga (I think) alluded to that could be several packages on an interposer rather than a monolithic massive single chip (I don't think HBM for example can be incorporated on die).

 

[-Fran-]

I agree with you on this, that doesn't look outside the realms for a server part. Also keep in mind that with the new interposer designs as Juanrga (I think) alluded to that could be several packages on an interposer rather than a monolithic massive single chip (I don't think HBM for example can be incorporated on die).

Depends on what they want to do with HBM. If you go back to the "root" of what HBM really is underneath, it's just another piece of silicon you can slap anywhere with tweaks.

In particular, I can totally see they adding just 1 layer of HBM using HBMv2 with a single layer, 1/2GB of "L4" memory, instead of eMMC like Intel. For the amount of SPs you can pack into an APU, more than 2GB would be overkill, isn't it?

Ahhh, the possibilities you can think when looking at block diagrams, haha.

Cheers!

 

[8350rocks]

Can we define a bit better what "big" means?

I ask that because Fiji is also "big". And there, big means "maximum allowed for the process". I don't remember more details, but Fiji is pretty big and GPUs are usually pretty massive; same for the GM210. So, 300mm2? 500mm2? 600mm2?

That information (Fudz'es) might go on several ways in terms of speculation. Well, if you want to believe it in part at least, haha.

My first road is making the CPU 50/40 (not like 30/50) of die space (leaving ~10% for the IMC and other stuff), packing those 32MB of L3 dwarfing everything else, except the GPU. It would be a 125W part or a 65W for Servers? Since they won't need to clock it high (that's the idea of departing from Dozer), even though it's "big" should be around current Xeons in terms of power at least.

Another road is not trusting there are 8MB and it's 4MB or 6MB per 2 cores, giving a more known "proportion" for the CPU size. The GPU will still be massive if they're aiming to do a server APU.

And the 3rd road is the GPU will be minimal and the CPU will use most of the available space. In my mind this would be a 65/25 split.

So, we have to make the connection with available process nodes they will be targeting and just put some numbers around transistor size for cache and assuming the GPU will stay more or less the same (in terms of transistors) against Carrizo's iGPU... I guess.

Cheers!

Yuka, my best guess would put that somewhere in the neighborhood of 600mm^2-ish monolithic die with all that hardware...would be massive...

 

[Cazalan]

Samsung finally jumping into the HBM fray with mass production in early 2016. Looks like they're jumping straight to HBM2.

2/4/8GB parts with 256GB/s bandwidth

Expecting ASICs to use up to 6 on the package with 1.5TB/s total bandwidth.

http://www.computerbase.de/2015-08/idf-2015-samsung-fertigt-high-bandwidth-memory-ab-2016/

 

[de5_Roy]

i was gonna post that! ;-;
so here's the wccftenglish.com's er.. interpretation
Samsung Enters The HBM Market In 1H 2016 - HPC and GPU Ready HBM With Up to 1.5 TB/s Bandwidth and 48 GB VRAM
http://wccftech.com/samsung-enters-hbm-market-1h-2016-hpc-gpu-ready-hbm-15-tbs-bandwidth-48-gb-vram/

H1 2016 is quite promising.

 

[gamerk316]

So basically, the near bankrupt AMD did all the R&D for Samsung/NVIDIA?

 

[jdwii]

So basically, the near bankrupt AMD did all the R&D for Samsung/NVIDIA?

Basically, but in the end it will probably pay off for Amd

 

[jimmysmitty]

So basically, the near bankrupt AMD did all the R&D for Samsung/NVIDIA?

Except that HBM is based on Wide I/O which was already developed by Samsung so AMD just adopted it to GPUs.

 

[jdwii]

When do you guys think we will see HBM on budget APUs?