AMD CPUs, SoC Rumors and Speculations Temp. thread 2

[jdwii]

Why aren't people posting this, this is great news for Amd

http://arstechnica.com/gaming/2016/04/amd-promises-three-new-gaming-processors-coming-soon-is-one-for-xbox/

New china deal
http://www.marketwatch.com/story/amds-stock-has-best-day-in-40-years-after-china-jv-deal-q1-results-2016-04-22

 

[Cazalan]

Hans Mosesmann, Raymond James & Associates, Inc. - Analyst [14]

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Can you give us a sense on Zen, based on you're hitting all your performance milestones, what part of the server market are you addressing? What's the size of the opportunity? And I am assuming that you can go after both enterprise and data center because it is an x86. Thanks.

Lisa Su, AMD - President and CEO [15]

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Yes. We are pleased with the progress on Zen. Obviously, there are lots of engineering milestones to pass, but a key one is that we are on track to sample to our priority customers in the second quarter.

In terms of the markets that we can address, yes, we do believe that Zen has broad applicability across enterprise and data center. And we will continue to work with both OEMs and ODMs to ensure that they have the right boards and platforms for our products.

Pertinent Zen info. Sampling to tier 1 customers in Q2.

 

[8350rocks]

Recent AMD News about product launches/benchmarks: http://www.guru3d.com/news-story/amd-radeon-r9-480-perf-is-close-to-r9-390x.html

 

[jimmysmitty]

I like how the latest rumor for AMDs GPUs involves a mobile benchmark that is not nearly as pertinent to us.

Can't wait to see how well Zen handles AnTuTu.....

 

[cdrkf]

Some more info on Zen:
https://www.kitguru.net/components/cpu/matthew-wilson/amd-to-focus-on-8-core-dies-for-first-zen-processors/

edit: original source:
http://wccftech.com/amd-only-fabricating-octa-core-zen-x86-die/

Makes sense for them to not produce too many different dies to start with. I'm not convinced by the argument this means only 6 and 8 core parts however. New design on new node = lots of defects. On that basis personally I think we'll see some harvested quad core parts as the entry level version of Zen (especially given none of the APU's will offer more than 2 core / 4 threads- going from 4 threads to 12 leaves a big gap on the line up).

This also suggests next years APU is going to get a serious boost if it's a quad core (8 thread) zen based part.

 

[juanrga]

Some more info on Zen:
https://www.kitguru.net/components/cpu/matthew-wilson/amd-to-focus-on-8-core-dies-for-first-zen-processors/

edit: original source:
http://wccftech.com/amd-only-fabricating-octa-core-zen-x86-die/

Makes sense for them to not produce too many different dies to start with. I'm not convinced by the argument this means only 6 and 8 core parts however. New design on new node = lots of defects. On that basis personally I think we'll see some harvested quad core parts as the entry level version of Zen (especially given none of the APU's will offer more than 2 core / 4 threads- going from 4 threads to 12 leaves a big gap on the line up).

This also suggests next years APU is going to get a serious boost if it's a quad core (8 thread) zen based part.

The original source is not WCCFTECH, but certain Italian site.

8-core dies was just what someone I know predicted 😀

I agree with 8-core and 6-core hypothesis. Consider that a 4-core chip would mean that half the die is damaged. Yields cannot be that bad!

 

[8350rocks]

Some more info on Zen:
https://www.kitguru.net/components/cpu/matthew-wilson/amd-to-focus-on-8-core-dies-for-first-zen-processors/

edit: original source:
http://wccftech.com/amd-only-fabricating-octa-core-zen-x86-die/

Makes sense for them to not produce too many different dies to start with. I'm not convinced by the argument this means only 6 and 8 core parts however. New design on new node = lots of defects. On that basis personally I think we'll see some harvested quad core parts as the entry level version of Zen (especially given none of the APU's will offer more than 2 core / 4 threads- going from 4 threads to 12 leaves a big gap on the line up).

This also suggests next years APU is going to get a serious boost if it's a quad core (8 thread) zen based part.

The original source is not WCCFTECH, but certain Italian site.

8-core dies was just what someone I know predicted 😀

I agree with 8-core and 6-core hypothesis. Consider that a 4-core chip would mean that half the die is damaged. Yields cannot be that bad!

I would be surprised to not see at least some entry level quad cores, even if they were just Zen APUs with disabled iGPU.

 

[juanrga]

Some more info on Zen:
https://www.kitguru.net/components/cpu/matthew-wilson/amd-to-focus-on-8-core-dies-for-first-zen-processors/

edit: original source:
http://wccftech.com/amd-only-fabricating-octa-core-zen-x86-die/

Makes sense for them to not produce too many different dies to start with. I'm not convinced by the argument this means only 6 and 8 core parts however. New design on new node = lots of defects. On that basis personally I think we'll see some harvested quad core parts as the entry level version of Zen (especially given none of the APU's will offer more than 2 core / 4 threads- going from 4 threads to 12 leaves a big gap on the line up).

This also suggests next years APU is going to get a serious boost if it's a quad core (8 thread) zen based part.

The original source is not WCCFTECH, but certain Italian site.

8-core dies was just what someone I know predicted 😀

I agree with 8-core and 6-core hypothesis. Consider that a 4-core chip would mean that half the die is damaged. Yields cannot be that bad!

I would be surprised to not see at least some entry level quad cores, even if they were just Zen APUs with disabled iGPU.

We are discussing the 8-core die for HEDT CPUs, not latter APUs.

 

[-Fran-]

We are discussing the 8-core die for HEDT CPUs, not latter APUs.

Remember they will use the same socket... In theory.

So, they could just fill the gap with Excavator and harvested APUs. 4 module APUs could exist? I doubt it, but oh well.

I do agree on the void though. But I would imagine we will see the "Rana" effect again. I'm waiting for news of buying a 6 core part that can be turned into an 8 core 😛

Cheers!

 

[juanrga]

We are discussing the 8-core die for HEDT CPUs, not latter APUs.

Remember they will use the same socket... In theory.

So, they could just fill the gap with Excavator and harvested APUs. 4 module APUs could exist? I doubt it, but oh well.

I do agree on the void though. But I would imagine we will see the "Rana" effect again. I'm waiting for news of buying a 6 core part that can be turned into an 8 core 😛

Cheers!

Common socket AM4 is only confirmed for Excavator APUs and Zen CPUs. It is not known if latter Zen APUs will be AM4 compatible or will require a new socket (AM4+? AM5?)

The Zen APUs don't use the 8-core die of the Zen CPU either. Recall we are here discussing the feasibility of 4-core CPUs obtained from a half damaged 8-core die!

 

[prtskg]

I thought it was already known that 8 core parts will come first and others follow later.

 

[8350rocks]

I thought it was already known that 8 core parts will come first and others follow later.

Certainly flagship first...just discussing about how low the core counts will get on the entry binned parts.

 

[Vogner16]

We are discussing the 8-core die for HEDT CPUs, not latter APUs.

Remember they will use the same socket... In theory.

So, they could just fill the gap with Excavator and harvested APUs. 4 module APUs could exist? I doubt it, but oh well.

I do agree on the void though. But I would imagine we will see the "Rana" effect again. I'm waiting for news of buying a 6 core part that can be turned into an 8 core 😛

Cheers!

Common socket AM4 is only confirmed for Excavator APUs and Zen CPUs. It is not known if latter Zen APUs will be AM4 compatible or will require a new socket (AM4+? AM5?)

The Zen APUs don't use the 8-core die of the Zen CPU either. Recall we are here discussing the feasibility of 4-core CPUs obtained from a half damaged 8-core die!

This wouldn't be done as amd has been ever since kaveri on the HSA path. aka they wont salvage a 4 core damaged die and put it on the same APU chip as a small gpu much like early intel i5's (430m) as that is an out dated way to make an apu and would not hit the performance needed for the part with those specs to hit

most likely we wont see 4 core zen cpu's from damaged die's until much later unless yields are really bad and even then I only expect to see them for OEM's.

 

[-Fran-]

When I mentioned "the Rana effect", I didn't mean disabling due to yields, but due to market needs. Come on fellas! Don't you all remember the glorious "core unlocking" days of the Phenom II 560BE?

I will concede that the first batch, *if* they decide to go as low as 4 cores per CPU would most likely be to yields, but down the road, they might as well disable them manually to just sell more CPUs. There are a lot of assumptions under what I am saying, I know, but it's not *that* far-fetched. They already did it once, so why not twice?

Also, at 14nm, I would imagine making a 4 module+12 CU part is not *that* hard? They already optimized for density, so they would be able to squeeze more modules, right? At least, 3 modules + 10 CU is perfectly possible even at 28nm.

Cheers! 😛

 

[Vogner16]

When I mentioned "the Rana effect", I didn't mean disabling due to yields, but due to market needs. Come on fellas! Don't you all remember the glorious "core unlocking" days of the Phenom II 560BE?

I will concede that the first batch, *if* they decide to go as low as 4 cores per CPU would most likely be to yields, but down the road, they might as well disable them manually to just sell more CPUs. There are a lot of assumptions under what I am saying, I know, but it's not *that* far-fetched. They already did it once, so why not twice?

Also, at 14nm, I would imagine making a 4 module+12 CU part is not *that* hard? They already optimized for density, so they would be able to squeeze more modules, right? At least, 3 modules + 10 CU is perfectly possible even at 28nm.

Cheers! 😛

even 4 module 20 CU is possible on 28nm just nobody will do it because of the memory bandwidth issues and the expense of making such a part... the APU game is all about price to performance. it has to be cheaper to make than separate chips.

 

[juanrga]

We are discussing the 8-core die for HEDT CPUs, not latter APUs.

Remember they will use the same socket... In theory.

So, they could just fill the gap with Excavator and harvested APUs. 4 module APUs could exist? I doubt it, but oh well.

I do agree on the void though. But I would imagine we will see the "Rana" effect again. I'm waiting for news of buying a 6 core part that can be turned into an 8 core 😛

Cheers!

Common socket AM4 is only confirmed for Excavator APUs and Zen CPUs. It is not known if latter Zen APUs will be AM4 compatible or will require a new socket (AM4+? AM5?)

The Zen APUs don't use the 8-core die of the Zen CPU either. Recall we are here discussing the feasibility of 4-core CPUs obtained from a half damaged 8-core die!

This wouldn't be done as amd has been ever since kaveri on the HSA path. aka they wont salvage a 4 core damaged die and put it on the same APU chip as a small gpu much like early intel i5's (430m) as that is an out dated way to make an apu and would not hit the performance needed for the part with those specs to hit

most likely we wont see 4 core zen cpu's from damaged die's until much later unless yields are really bad and even then I only expect to see them for OEM's.

AMD will start with 8-core dies and we will see 8-core and 6-core CPUs. It is difficult to wait 4-core CPUs because it would mean 50% of the die is damaged, which is a lot of! Latter (~8 months) I expect AMD to release a 4-core die for the consumer Zen APUs.

 

[juanrga]

When I mentioned "the Rana effect", I didn't mean disabling due to yields, but due to market needs. Come on fellas! Don't you all remember the glorious "core unlocking" days of the Phenom II 560BE?

I will concede that the first batch, *if* they decide to go as low as 4 cores per CPU would most likely be to yields, but down the road, they might as well disable them manually to just sell more CPUs. There are a lot of assumptions under what I am saying, I know, but it's not *that* far-fetched. They already did it once, so why not twice?

Also, at 14nm, I would imagine making a 4 module+12 CU part is not *that* hard? They already optimized for density, so they would be able to squeeze more modules, right? At least, 3 modules + 10 CU is perfectly possible even at 28nm.

Current AMD is a different company now than then. And the 14nm FinFET node is much more expensive and sophisticated than 45nm planar. The PC market is different as well. Zen CPU targets HEDT and that mean 8-core (with 6-core due to yields). It is difficult to think on a quad-core CPU for HEDT, when quad-core is mainstream APU. I remark again it is difficult to accept 50% defective dies. Yields cannot be so bad and financial position of AMD makes me to be reluctant they can fabricate 8-core dies and disable half of them on purpose.

Not sure what you mean by modules. Zen is not a CMT design.

 

[-Fran-]

Current AMD is a different company now than then. And the 14nm FinFET node is much more expensive and sophisticated than 45nm planar. The PC market is different as well. Zen CPU targets HEDT and that mean 8-core (with 6-core due to yields). It is difficult to think on a quad-core CPU for HEDT, when quad-core is mainstream APU. I remark again it is difficult to accept 50% defective dies. Yields cannot be so bad and financial position of AMD makes me to be reluctant they can fabricate 8-core dies and disable half of them on purpose.

Not sure what you mean by modules. Zen is not a CMT design.

I agree on Yields, but you never really know until they hit the market. Plus, weren't some rumors about the process being really bad?

And I meant APUs when mentioning modules. I still believe they could go with 3 or 4 Excavator modules and slap a lower amount of CUs/SPs into the APU to fill in a market gap.

Like you say though, it will really depend if it makes sense economically. Intel i5s still sell like hot cakes, so leaving a whole in that segment might not be such a good idea either.

Cheers!

 

[juanrga]

Current AMD is a different company now than then. And the 14nm FinFET node is much more expensive and sophisticated than 45nm planar. The PC market is different as well. Zen CPU targets HEDT and that mean 8-core (with 6-core due to yields). It is difficult to think on a quad-core CPU for HEDT, when quad-core is mainstream APU. I remark again it is difficult to accept 50% defective dies. Yields cannot be so bad and financial position of AMD makes me to be reluctant they can fabricate 8-core dies and disable half of them on purpose.

Not sure what you mean by modules. Zen is not a CMT design.

I agree on Yields, but you never really know until they hit the market. Plus, weren't some rumors about the process being really bad?

EEtimes said that Samsung yields were above 70% then. The problem was Glofo, which couldn't improve yields fast enough for Apple chips, when Apple did launch new iphone. I don't see any reason why Glofo couldn't have good yields for Zen launch.

And I meant APUs when mentioning modules. I still believe they could go with 3 or 4 Excavator modules and slap a lower amount of CUs/SPs into the APU to fill in a market gap.

Like you say though, it will really depend if it makes sense economically. Intel i5s still sell like hot cakes, so leaving a whole in that segment might not be such a good idea either.

I was discussing Zen-based APUs.

 

[juanrga]

Possibly the first die shot of Zen

It looks like two clusters of quad-cores with private L2 and shared L3. It seems that the L3 in each cluster is partitioned into two regions, one region of 4MB for each pair of cores. It seems there are two memory controllers, one per cluster. This all agrees with expected configuration for Summit.

 

[jimmysmitty]

Possibly the first die shot of Zen

It looks like two clusters of quad-cores with private L2 and shared L3. It seems that the L3 in each cluster is partitioned into two regions, one region of 4MB for each pair of cores. It seems there are two memory controllers, one per cluster. This all agrees with expected configuration for Summit.

If the L3 is split, is it accessible to each cluster or only to the cluster it is assigned?

Cache is always one thing Intel is ahead of AMD on. If I remember their current L3 cache is one large cache that all cores can access.

 

[juanrga]

Possibly the first die shot of Zen

It looks like two clusters of quad-cores with private L2 and shared L3. It seems that the L3 in each cluster is partitioned into two regions, one region of 4MB for each pair of cores. It seems there are two memory controllers, one per cluster. This all agrees with expected configuration for Summit.

If the L3 is split, is it accessible to each cluster or only to the cluster it is assigned?

Cache is always one thing Intel is ahead of AMD on. If I remember their current L3 cache is one large cache that all cores can access.

Cannot say from that image. But if the L3 is accessible globally the latencies will vary a lot of and the cache manager would try to store data/instructions locally (aka in its own cluster) for faster access from cores.

 

[jimmysmitty]

Possibly the first die shot of Zen

It looks like two clusters of quad-cores with private L2 and shared L3. It seems that the L3 in each cluster is partitioned into two regions, one region of 4MB for each pair of cores. It seems there are two memory controllers, one per cluster. This all agrees with expected configuration for Summit.

If the L3 is split, is it accessible to each cluster or only to the cluster it is assigned?

Cache is always one thing Intel is ahead of AMD on. If I remember their current L3 cache is one large cache that all cores can access.

Cannot say from that image. But if the L3 is accessible globally the latencies will vary a lot of and the cache manager would try to store data/instructions locally (aka in its own cluster) for faster access from cores.

Yes if the cache is set to 4MB per "cluster" then each "cluster" would benefit from storing and accessing its own cache vs having to "cross the stream" to access the other "clusters cache".

If it is that way then I would assume under heavy loads that utilize cache more it would start to hit a bottleneck when the "clusters" have to start storing data in the other cache.

This is all theory. I would hope that AMD would not only learn from but levy their cross license agreement with Intel and utilize some of Intels cache ideas as again, Intel has always had faster cache than AMD even when Athlon 64 was faster than Pentium 4.

 

[Vogner16]

http://wccftech.com/amd-zen-cpu-performance-double-fx-8350/

die shot and some comments from amd listed on this. also show that die shot with some blocks drawn in to show where modules sit. this design is very similar to intels latest Broadwell EP cpu

 

[jimmysmitty]

http://wccftech.com/amd-zen-cpu-performance-double-fx-8350/

die shot and some comments from amd listed on this. also show that die shot with some blocks drawn in to show where modules sit. this design is very similar to intels latest Broadwell EP cpu

Yay hype.

Should be a fun few months.