AMD CPUs, SoC Rumors and Speculations Temp. thread 2

[8350rocks]

What frequency supports the memory controller on Bristol Ridge? 2400MHz? 3600MHz?

Not sure about that, never asked.

 

[juanrga]

Once the process is more mature, possibly close to 4 GHz if it turns out quite well.

if 4GHz and higher clocks were reachable on the 14LPP then IBM had chosen that process for its new Power9 CPU. Instead IBM chose 14HP.

LPP --> Low Power Plus

HP --> High Performance

 

[sleeper357]

2.4ghz base= 14nm LPE ----Low power early
3Ghz base=14nm LPP----Low power plus
http://www.globalfoundries.com/technology-solutions/leading-edge-technology/14-lpe-lpp

I base this off reports BY amd taking a 33mil write off for LPE, even stating that lpe had meet all targets. At least that is how i understood it. based on this article they are both out there in volume production
According to Expreview the 14nm process consists of LPE (low-power early) and the LPP (Low Power Plus, advanced low power processing) and both are being churned out at the New York, Malta, Fab 8 wafer fab production.

 

[David_24]

MERGED QUESTION
Question from David_24 : "What are your expectations about how zen will compete with intel in gaming and high end workstations?"

just a brief discussion on zen and what your expectations are so far.

will the 8 cores have something similar to hyper threading?
will the pricing be very aggressive from amd?
will it compete well with the i5 for gaming?
Will gaming come to use the extra cores over the next 3 years?

 

[cdrkf]

MERGED QUESTION
Question from David_24 : "What are your expectations about how zen will compete with intel in gaming and high end workstations?"

just a brief discussion on zen and what your expectations are so far.

will the 8 cores have something similar to hyper threading?
will the pricing be very aggressive from amd?
will it compete well with the i5 for gaming?
Will gaming come to use the extra cores over the next 3 years?

To your questions:

1: will the 8 cores have something similar to hyper threading? Yes, confirmed by AMD as 8 cores, 16 threads

2: will the pricing be very aggressive from amd? Unknown- but this is a big chip and AMD have made comparisons against intels 'E' platform so expect it in that price segment, NOT competing against £150 - £200 i5 (at least for 8 core). I'd guess there will be a cut down chip as a 'value' leader, but I'd expect quad cores due next year to be more targeted at budget.

3: will it compete well with the i5 for gaming? Ish- per core performance should be there, but probably not offer as good value- you don't usually need to purchase a 6 or 8 core cpu for games as it stands.

4: Will gaming come to use the extra cores over the next 3 years? Yes definitely. There are plenty of games that already take advantage of 8 thread i7's over the 4 thread i5. The fact that consoles are 8 thread designs I think is helping to get devs thinking about thread usage more. Also DX12 and Vulkan allow use of more threads. It will take a few years though.

 

[salgado18]

Once the process is more mature, possibly close to 4 GHz if it turns out quite well.

if 4GHz and higher clocks were reachable on the 14LPP then IBM had chosen that process for its new Power9 CPU. Instead IBM chose 14HP.

LPP --> Low Power Plus

HP --> High Performance

But IBM is not targeting low-power devices, like Zen is. AMD said they want it to be scalable from very low to high, and I believe 14HP would not be as good with low-power targets, like sub-15W CPUs.

 

[8350rocks]

Once the process is more mature, possibly close to 4 GHz if it turns out quite well.

if 4GHz and higher clocks were reachable on the 14LPP then IBM had chosen that process for its new Power9 CPU. Instead IBM chose 14HP.

LPP --> Low Power Plus

HP --> High Performance

But IBM is not targeting low-power devices, like Zen is. AMD said they want it to be scalable from very low to high, and I believe 14HP would not be as good with low-power targets, like sub-15W CPUs.

True...Power9 TDP is likely, at minimum, almost double the estimated flagship TDP for Zen.

 

[juanrga]

Once the process is more mature, possibly close to 4 GHz if it turns out quite well.

if 4GHz and higher clocks were reachable on the 14LPP then IBM had chosen that process for its new Power9 CPU. Instead IBM chose 14HP.

LPP --> Low Power Plus

HP --> High Performance

But IBM is not targeting low-power devices, like Zen is. AMD said they want it to be scalable from very low to high, and I believe 14HP would not be as good with low-power targets, like sub-15W CPUs.

What I have been stating for a while is that different needs require different process nodes. Precisely the point was that 14LPP is optimized for mobile means that it is not optimized for High Performance, reason why IBM is going the 14HP route for its own >4GHz CPUs.

 

[juanrga]

Power9 TDP is likely, at minimum, almost double the estimated flagship TDP for Zen.

What is the TDP for 24C Power9? And what is the TDP for 32C Zen?

 

[8350rocks]

Power9 8 core has TDP 150W

Power9 16 core has TDP 200W

Power9 24C has TDP 250W

Zen 8 core has TDP 95W

 

[Cazalan]

Zen running Doom.

https://www.youtube.com/watch?v=-IyrR8KsSfQ

 

[salgado18]

Zen running Doom.

https://www.youtube.com/watch?v=-IyrR8KsSfQ

That guy is... terrible at Doom? XD

Also, bad video aside, it only shows that the processor is basically ready, right?

 

[-Fran-]

That guy is... terrible at Doom? XD

Also, bad video aside, it only shows that the processor is basically ready, right?

You can't even extrapolate that much from what you see there, haha. The "smoothness" can't be measured correctly from the video itself and you can't even be sure AMD is using a *Zen* variant in it; I know it is heavily implied, but you never know for sure, right?

What you can say for sure, whoever was playing DOOM in that video, sucked, haha.

Cheers!

 

[jimmysmitty]

If Zen is clocked at 2.4GHz it is not the end of the world unless they are on par with Intel per clock with too old of a generation of CPU, especially since Intels 14nm is hitting base clocks of 4GHz.

I think it is better for this discussion if we use the clocks of the 8-core Intel cpu against 8-core Zen, which is 3.2GHz base and 3.7GHz turbo (i7-6900k). We can't mix 8-cores from AMD against 4-cores from Intel.

And why not? We currently do, FX 8350 vs an i7 or even an i5.

I agree though as that will be the market they will try to compete in but even so Intel has a clear clock speed advantage if the 2.4GHz is a top end clock speed. We wont know until closer to release.

Of course the real fun is in the fact that this has done nothing but fuel more rumors and it will eventually fuel more until release causing more crap than needs be.

If I can make 1 prediction- Zen 'top' clock speed isn't going to be 2.4ghz. Looking at this logically, there'd be 0 point in AMD developing and launching an 'almost as high IPC' as Intel with a serious clock speed deficit. That wouldn't gain them anything from where they are now.

Now, I can accept that base clocks could possibly be sub 3ghz (at least on the 8 core parts), however in that case I expect aggressive boost frequencies. I'd also think we'd see higher tdp parts than 95w if the clocks are that low (I mean again AMD have proven they'll push power in order to be performance competitive repeatedly in the past, typically going up to 140W if we ignore the 220w 9590).

AMD are expecting to be 'competitive' with equivalent Intel parts- that to me suggests we should see something close to Intels 8 core. That would suggest base clock in the low 3ghz ballpark. I mean the *current* engineering samples are at 2.4ghz already, and engineering samples are always pretty low clocked compared to a consumer product.

Edit: To put this another way doing a little bit of *very rough math*

The FX 8350 scores 1.1 in the Cinebench 11.5 single thread test. Assuming (generously) that Zen IPC is 1.6x that of Vishera (as the 40% is above Excavator), then at the same speed (4ghz) Zen would score a respectable 1.76 points.

Now if we state that the maximum frequency for Zen is just 2.4 ghz, then the Zen ST score would be just 1.06 points, i.e. slower in real terms than the current FX cpu. That wouldn't be a worthwhile product for them to launch.

Zen ES has 2.4 clockspeed at the moment. At this same point in the lifecycle of BD/PD, ES clocks were the same.

Food for thought...clocks will improve.

But Zen and BD are vastly different designs, one big difference being that BD was a long pipeline design with higher clock speed potential and Zen is a short pipeline, lower clock speed potential. Not saying they wont just saying that I doubt they will reach BD speeds and they wont need them if the IPC is decent anyways.

Zen running Doom.

https://www.youtube.com/watch?v=-IyrR8KsSfQ

AMD is not really good with marketing. They still have yet to come up with a memorable jingle.

That was a meh teaser and yea that guy stinks at playing Doom.

 

[cdrkf]

@jimmy, as far as I'm aware we don't actually know the pipeline length for Zen? I'm expecting it to be a bit shorter than BD, but if you look at Intel's latest designs they use moderate length pipelines with a lot of tech to circumvent the potential penalties (e.g. uOP cache, hyper threading etc).

It will be interesting to hopefully get a deep dive on the Zen core design once it gets released. I'm hoping for a proper info / review release this year, even if the actual parts aren't available until Q1 2017.

 

[juanrga]

Power9 TDP is likely, at minimum, almost double the estimated flagship TDP for Zen.

What is the TDP for 24C Power9? And what is the TDP for 32C Zen?

Power9 8 core has TDP 150W

Power9 16 core has TDP 200W

Power9 24C has TDP 250W

Zen 8 core has TDP 95W

I asked for the TDP of the 32C Zen because I want to compare server to server, not server to desktop. According to Fudzilla the 32C Zen is a 180W chip and 250/180 = 1.39. Therefore Power9 TDP is not the double of flagship Zen.

 

[-Fran-]

Power9 TDP is likely, at minimum, almost double the estimated flagship TDP for Zen.

What is the TDP for 24C Power9? And what is the TDP for 32C Zen?

Power9 8 core has TDP 150W

Power9 16 core has TDP 200W

Power9 24C has TDP 250W

Zen 8 core has TDP 95W

I asked for the TDP of the 32C Zen because I want to compare server to server, not server to desktop. According to Fudzilla the 32C Zen is a 180W chip and 250/180 = 1.39. Therefore Power9 TDP is not the double of flagship Zen.

That is silver lining though. "Zen" means many many things, remember that XD

In your particular mini-discussion, you mixed process nodes for the broader picture including IBM to exemplify it's not suited for high performance in servers (14LPP vs 14HP), but Zen is going to share the process node across all products, including consumer; IBM is not under that "pressure".

Since the newest leak points to the dual package (MCM?) Opteron based on Zen will be 180W for a 16C/32T, puts it in line with the 95W TDP of the consumer 8C/16T part. Notice the Power9 projected speeds are under 4ghz, from what I could gather.

Cheers!

 

[juanrga]

Power9 TDP is likely, at minimum, almost double the estimated flagship TDP for Zen.

What is the TDP for 24C Power9? And what is the TDP for 32C Zen?

Power9 8 core has TDP 150W

Power9 16 core has TDP 200W

Power9 24C has TDP 250W

Zen 8 core has TDP 95W

I asked for the TDP of the 32C Zen because I want to compare server to server, not server to desktop. According to Fudzilla the 32C Zen is a 180W chip and 250/180 = 1.39. Therefore Power9 TDP is not the double of flagship Zen.

That is silver lining though. "Zen" means many many things, remember that XD

In your particular mini-discussion, you mixed process nodes for the broader picture including IBM to exemplify it's not suited for high performance in servers (14LPP vs 14HP), but Zen is going to share the process node across all products, including consumer; IBM is not under that "pressure".

Since the newest leak points to the dual package (MCM?) Opteron based on Zen will be 180W for a 16C/32T, puts it in line with the 95W TDP of the consumer 8C/16T part. Notice the Power9 projected speeds are under 4ghz, from what I could gather.

Cheers!

I am not asking why AMD chose 14LPP. I am asking just the opposite. I am asking why IBM engineers would chose an exotic and expensive 14HP if 14LPP is to good like some believe. It seems obvious to me that IBM engineers chose the High Performance process because can hit higher clocks whereas the Low Power Plus process cannot. This agrees with what The Stilt and Thevenin have said about 14LPP and Zen low clocks.

There is no leak about a dual package (MCM) Zen Opteron. Fudilla is speculating that the 32C Zen is a dual-die MCM package. Myself, I speculated more than one year ago that the 32C Zen would be made of four CPU dies on interposer and that the Zen APU would have two CPU dies and two GPU dies

http://semiaccurate.com/forums/showpost.php?p=233677&postcount=422

Desdrenboy has analyzed last Fudzilla slide about Zen APU and concluded it is showing a quad-die configuration with two CPU dies and two GPU dies

His speculation gives some extra weight to my early speculation, but being rigorous, we don't know still if the 32C CPU is 4x8-core or 2x16-core.

180W is not the TPD for a 16C/32T. 180W is the TPD for the 32C/64T.

Where do you got the "under 4ghz" for Power9?

 

[-Fran-]

I am not asking why AMD chose 14LPP. I am asking just the opposite. I am asking why IBM engineers would chose an exotic and expensive 14HP if 14LPP is to good like some believe. It seems obvious to me that IBM engineers chose the High Performance process because can hit higher clocks whereas the Low Power Plus process cannot. This agrees with what The Stilt and Thevenin have said about 14LPP and Zen low clocks.

There is no leak about a dual package (MCM) Zen Opteron. Fudilla is speculating that the 32C Zen is a dual-die MCM package. Myself, I speculated more than one year ago that the 32C Zen would be made of four CPU dies on interposer and that the Zen APU would have two CPU dies and two GPU dies

http://semiaccurate.com/forums/showpost.php?p=233677&postcount=422

Desdrenboy has analyzed last Fudzilla slide about Zen APU and concluded it is showing a quad-die configuration with two CPU dies and two GPU dies

His speculation gives some extra weight to my early speculation, but being rigorous, we don't know still if the 32C CPU is 4x8-core or 2x16-core.

180W is not the TPD for a 16C/32T. 180W is the TPD for the 32C/64T.

Where do you got the "under 4ghz" for Power9?

I can't find the article, but it was speculation. IBM got in bed with the USA DoD and Google, so they want improvements on top of Power8 and not something entirely new. So, the point was "keep the same power envelope, increase efficiency". Since the arch is supposed to run in high density farms, they need a process that can survive for long and no need to scale it down. This last part brings me to answer your question: IBM chose it because it won't target low power, only high power/density with it. AMD looks to have a unique manufacturing node. I wonder if Intel is using the same exact node for both -E and non-E CPUs though...

I know, because we're thinking of buying a couple to replace some of the old MF stuff with the new Power9 based CPUs 😛

And thanks for the correction on the Zen server CPU (Opteron still? xD); I read it wrong. So, it's going to be low clocked for sure. I wonder how much...

Cheers!

 

[juanrga]

Spoiler

I am not asking why AMD chose 14LPP. I am asking just the opposite. I am asking why IBM engineers would chose an exotic and expensive 14HP if 14LPP is to good like some believe. It seems obvious to me that IBM engineers chose the High Performance process because can hit higher clocks whereas the Low Power Plus process cannot. This agrees with what The Stilt and Thevenin have said about 14LPP and Zen low clocks.

There is no leak about a dual package (MCM) Zen Opteron. Fudilla is speculating that the 32C Zen is a dual-die MCM package. Myself, I speculated more than one year ago that the 32C Zen would be made of four CPU dies on interposer and that the Zen APU would have two CPU dies and two GPU dies

http://semiaccurate.com/forums/showpost.php?p=233677&postcount=422

Desdrenboy has analyzed last Fudzilla slide about Zen APU and concluded it is showing a quad-die configuration with two CPU dies and two GPU dies

His speculation gives some extra weight to my early speculation, but being rigorous, we don't know still if the 32C CPU is 4x8-core or 2x16-core.

180W is not the TPD for a 16C/32T. 180W is the TPD for the 32C/64T.

Where do you got the "under 4ghz" for Power9?

I can't find the article, but it was speculation. IBM got in bed with the USA DoD and Google, so they want improvements on top of Power8 and not something entirely new. So, the point was "keep the same power envelope, increase efficiency". Since the arch is supposed to run in high density farms, they need a process that can survive for long and no need to scale it down. This last part brings me to answer your question: IBM chose it because it won't target low power, only high power/density with it. AMD looks to have a unique manufacturing node. I wonder if Intel is using the same exact node for both -E and non-E CPUs though...

I know, because we're thinking of buying a couple to replace some of the old MF stuff with the new Power9 based CPUs 😛

And thanks for the correction on the Zen server CPU (Opteron still? xD); I read it wrong. So, it's going to be low clocked for sure. I wonder how much...

Cheers!

I think everyone would agree that IBM chose 14HP because provides the high clocks that Power9 targets. About Intel, they have at least two versions of the 14nm node. The enthusiast CPUs use the P1272 process node whereas the mainstream mobile SoCs use P1273. The former is optimized for high speed and P1273 is optimized for density and low leakage.

Same happens with other foundries. Globalfoundries has three 14nm nodes and TSMC has two or three versions of the 16nm node. As mentioned before a single process cannot be optimized for being cheap, dense, efficient and high performance at same time.

The only reason why AMD chose 14LPP for all the chips is because AMD doesn't have enough money to select different process nodes. Going 14LPP only was a money-based decision not because of technical merits. The 14LPP node cannot compete in high performance with 14HP with 16FF+ or with 14P1271. The 14LPP cannot compete with 16FC or 14LPE in mobile. Thus AMD choice is going to hurt them sure, how much remains to see.

 

[cdrkf]

Spoiler

I am not asking why AMD chose 14LPP. I am asking just the opposite. I am asking why IBM engineers would chose an exotic and expensive 14HP if 14LPP is to good like some believe. It seems obvious to me that IBM engineers chose the High Performance process because can hit higher clocks whereas the Low Power Plus process cannot. This agrees with what The Stilt and Thevenin have said about 14LPP and Zen low clocks.

There is no leak about a dual package (MCM) Zen Opteron. Fudilla is speculating that the 32C Zen is a dual-die MCM package. Myself, I speculated more than one year ago that the 32C Zen would be made of four CPU dies on interposer and that the Zen APU would have two CPU dies and two GPU dies

http://semiaccurate.com/forums/showpost.php?p=233677&postcount=422

Desdrenboy has analyzed last Fudzilla slide about Zen APU and concluded it is showing a quad-die configuration with two CPU dies and two GPU dies

His speculation gives some extra weight to my early speculation, but being rigorous, we don't know still if the 32C CPU is 4x8-core or 2x16-core.

180W is not the TPD for a 16C/32T. 180W is the TPD for the 32C/64T.

Where do you got the "under 4ghz" for Power9?

I can't find the article, but it was speculation. IBM got in bed with the USA DoD and Google, so they want improvements on top of Power8 and not something entirely new. So, the point was "keep the same power envelope, increase efficiency". Since the arch is supposed to run in high density farms, they need a process that can survive for long and no need to scale it down. This last part brings me to answer your question: IBM chose it because it won't target low power, only high power/density with it. AMD looks to have a unique manufacturing node. I wonder if Intel is using the same exact node for both -E and non-E CPUs though...

I know, because we're thinking of buying a couple to replace some of the old MF stuff with the new Power9 based CPUs 😛

And thanks for the correction on the Zen server CPU (Opteron still? xD); I read it wrong. So, it's going to be low clocked for sure. I wonder how much...

Cheers!

I think everyone would agree that IBM chose 14HP because provides the high clocks that Power9 targets. About Intel, they have at least two versions of the 14nm node. The enthusiast CPUs use the P1272 process node whereas the mainstream mobile SoCs use P1273. The former is optimized for high speed and P1273 is optimized for density and low leakage.

Same happens with other foundries. Globalfoundries has three 14nm nodes and TSMC has two or three versions of the 16nm node. As mentioned before a single process cannot be optimized for being cheap, dense, efficient and high performance at same time.

The only reason why AMD chose 14LPP for all the chips is because AMD doesn't have enough money to select different process nodes. Going 14LPP only was a money-based decision not because of technical merits. The 14LPP node cannot compete in high performance with 14HP with 16FF+ or with 14P1271. The 14LPP cannot compete with 16FC or 14LPE in mobile. Thus AMD choice is going to hurt them sure, how much remains to see.

Actually I think choosing 14 LPP wasn't 'just money'... if that were the case 14 LPE would be cheaper by now given it's older. I think the reality is it's a compromise- it's the middle ground and as such will scale better for a wider range of products than either 14 LPE or 14HP would. Sure 14HP would be better for Zen desktop as it would likely allow a higher clock headroom- but servers usually want lower power consumption and more cores vs high clocks, and lets be honest that's where AMD will make most money.

The other thing to consider- there's nothing preventing AMD releasing an updated version of Zen on a different / improved process a year or so on. This should be the first of a series of cores, what is key to my mind is the fundamental design is good, the IPC is there- because those are things that are very hard to add in after the fact (just look at the comparative lack of progression with the Dozer cores, they got better, but even Excavator is still behind Sandy in IPC).

I also still don't think that the LPP process automatically means the clocks are going to be terrible.

 

[juanrga]

I didn't say that AMD chose 14LPP over 14LPE due to costs. My point was that "The only reason why AMD chose 14LPP for all the chips is because AMD doesn't have enough money to select different process nodes", with "nodes" in plural. Instead implementing each chip in the more adequate process node (mobile on 14LPE, enthusiast on 14HP) or some other combination, AMD is using a single process node for all the chips. And this is not a decision taken by technical reasons but by economic reasons.

There are different kind of servers. IBM is using 14HP because their servers target very high clocks. But I agree that AMD server CPUs will target lower clocks, probably the 32 core Zen could be clocked around 2GHz.

About LPP clocks, I am hearing from people as Thevenin that:

The 14nm LPP performs best (efficiency wise) up to 2.5GHz, and takes a significantly nose dive at frequencies above 3GHz. [...] Samsung 14nm LPE/P is a truly mobile / embedded / specialized ASIC optimized process.

 

[salgado18]

Don't forget that AMD wants Zen to serve desktop and servers, but also mobile and low power. I believe they want to replace Jaguar with Zen. So it must use low power process to achieve those targets. They probably went with 14LPP instead of 14HP or other high-power because of those mobile targets, not because of servers.

I also remember a slide from them showing they expected a growth in every market segment except desktop, which was declining in size year after year. They are targeting efficiency for mobile and servers first, and then desktop with that they can get out of it.

 

[8350rocks]

I didn't say that AMD chose 14LPP over 14LPE due to costs. My point was that "The only reason why AMD chose 14LPP for all the chips is because AMD doesn't have enough money to select different process nodes", with "nodes" in plural. Instead implementing each chip in the more adequate process node (mobile on 14LPE, enthusiast on 14HP) or some other combination, AMD is using a single process node for all the chips. And this is not a decision taken by technical reasons but by economic reasons.

There are different kind of servers. IBM is using 14HP because their servers target very high clocks. But I agree that AMD server CPUs will target lower clocks, probably the 32 core Zen could be clocked around 2GHz.

About LPP clocks, I am hearing from people as Thevenin that:

The 14nm LPP performs best (efficiency wise) up to 2.5GHz, and takes a significantly nose dive at frequencies above 3GHz. [...] Samsung 14nm LPE/P is a truly mobile / embedded / specialized ASIC optimized process.

Just to point out, you are quoting the same comment from a year ago...which was speculation then...and is speculation now.

As for IBM, as far as I am aware, Power9 top core count part runs at 2.5 GHz like Power8. As Yuka pointed out, they are after efficiency...not clockspeeds.

Additionally...LPP will have much better efficiency than that of 14HP, not to mention, GloFo does not even carry 14HP, either.

 

[juanrga]

Don't forget that AMD wants Zen to serve desktop and servers, but also mobile and low power. I believe they want to replace Jaguar with Zen. So it must use low power process to achieve those targets. They probably went with 14LPP instead of 14HP or other high-power because of those mobile targets, not because of servers.

I also remember a slide from them showing they expected a growth in every market segment except desktop, which was declining in size year after year. They are targeting efficiency for mobile and servers first, and then desktop with that they can get out of it.

Yes Zen replaces both Jaguar and Piledriver/Excavator. But my point wasn't that AMD would chose 14HP instead 14LPP. My point was other:

"The only reason why AMD chose 14LPP for all the chips is because AMD doesn't have enough money to select different process nodes", with "nodes" in plural. Instead implementing each chip in the more adequate process node (mobile on 14LPE, enthusiast on 14HP or some other combination), AMD is using a single process node for all the chips. And this is not a decision taken by technical reasons but by economic reasons.