News AMD is allegedly readying budget hexa-core Krackan Point APUs — Hybrid 3+3 core "Zen 5 + Zen 5c" offering surfaces at Geekbench

[Admin]

A six-core hybrid APU from AMD's Krackan Point family has been spotted at Geekbench.

AMD is allegedly readying budget hexa-core Krackan Point APUs — Hybrid 3+3 core "Zen 5 + Zen 5c" offering surfaces at Geekbench : Read more

 

[usertests]

Rest assured, laptops powered by AMD's Krackan Point offerings are set to arrive in early 2025 - starting at $799 if we go by leaks.

Lol pricing. It reminds me of AMD pitching Mendocino as a $700 laptop chip. Krackan/Kraken is clearly better than Memedocino, but not necessarily better than discounted Hawk Point systems on the market because of the graphics (8 CUs max).

VideoCardz hallucinated 4 CUs for the 6-core. There's nothing to corroborate that, but it could be correct. If true, it would at least match Phoenix2's CU count, but it would only be interesting if it was very cheap, say sub-$300.

I don't think consumers care at all for the NPU and Copilot+. AMD needs to invent some use cases if Microsoft is going to drop the ball for everybody. Get your own streaming video upscaler to use the NPU and convert 480p to 1080p/4K, and maybe leverage XDNA2 for FSR4. But the point is that this capability obviously not justify pushing systems with a tiny, cheap die to $700-800.

 

[Cooe]

Kraken will most DEFINITELY have all 8x cores (4x Zen 5+ 4x Zen 5c) on the same, single unified ring bus. There is quite literally ZERO technological reason for them not to. 🤷

Geekbench presenting them as two different clusters is just how it deals with multiple core types on any CPU, REGARDLESS of how they are laid out/connected internally on the chip itself! If the cores on a CPU are different from each other in ANY major spec (ISA support, cache sizes, etc...) then Geekbench will list them out as separate "clusters".

And the reason why AMD's Strix Point has two separate rings connected w/ crossbars (think old-school big die Xeon style, or AMD Zen 4/5c "dense" 16-core CCD style for a more modern example lol) instead of a single unified ring for all 12x cores didn't have ANYTHING to do with it having "two different "CPU core types" on the same CPU", and EVERYTHING to do with the fact that AMD's current ring bus tech (which originated on Zen 3 w/ its then new unified CCX's) cannot handle more than 8x cores on a ring... Aka the exact same number of cores on a standard Zen CCD.

AMD has made it repeatedly clear with their CPU die designs over the past couple years that anything >8-cores on a single die needs >1x ring bus + the extra crossbar links to connect them with their current bus technology. 🤷

(Again, see literally every Zen c/"dense" CCD design made so far AND Strix Point all having literally the EXACT SAME CPU bus layout! [Aka, 2x rings with each having ≈1/2 of the cores on it {or 1/2 the core area in Strix Point's case, as 4x Zen 5 ≈ roughly 8x Zen 5c in size}, and w/ 2x crossbars connecting between them.])

 

[subspruce]

Kraken will most DEFINITELY have all 8x cores (4x Zen 5+ 4x Zen 5c) on the same, single unified ring bus. There is quite literally ZERO technological reason for them not to. 🤷

Geekbench presenting them as two different clusters is just how it deals with multiple core types on any CPU, REGARDLESS of how they are laid out/connected internally on the chip itself! If the cores on a CPU are different from each other in ANY major spec (ISA support, cache sizes, etc...) then Geekbench will list them out as separate "clusters".

And the reason why AMD's Strix Point has two separate rings connected w/ crossbars (think old-school big die Xeon style, or AMD Zen 4/5c "dense" 16-core CCD style for a more modern example lol) instead of a single unified ring for all 12x cores didn't have ANYTHING to do with it having "two different "CPU core types" on the same CPU", and EVERYTHING to do with the fact that AMD's current ring bus tech (which originated on Zen 3 w/ its then new unified CCX's) cannot handle more than 8x cores on a ring... Aka the exact same number of cores on a standard Zen CCD.

AMD has made it repeatedly clear with their CPU die designs over the past couple years that anything >8-cores on a single die needs >1x ring bus + the extra crossbar links to connect them with their current bus technology. 🤷

(Again, see literally every Zen c/"dense" CCD design made so far AND Strix Point all having literally the EXACT SAME CPU bus layout! [Aka, 2x rings with each having ≈1/2 of the cores on it {or 1/2 the core area in Strix Point's case, as 4x Zen 5 ≈ roughly 8x Zen 5c in size}, and w/ 2x crossbars connecting between them.])

4+4 is going to be another SKU and 3+3 is going to be bottom of the barrel