AMD K6 vs. P3

[enforcer22]

K7 Athlon Thunderbird 1GHz, 03.06.2000

sorry for the double post but the thunderbird was AMD's second chip to be clocked at 1ghz

[edit] Athlon

[edit] Athlon Classic
-> K7 "Argon" (250 nm)
-> K75 "Pluto/Orion" (180 nm)
L1-Cache: 64 + 64 KiB (Data + Instructions)
L2-Cache: 512 KiB, external chips on CPU module with 50, 40 or 33% of CPU-speed
MMX, 3DNow!
Slot A (EV6)
Front side bus: 200 MT/s (100 MHz double-pumped)
VCore: 1.6 V (K7), 1.6 - 1.8 V (K75)
First release: June 23, 1999 (K7), November 29 1999 (K75)
Clockrate: 500 - 700 MHz (K7), 550 - 1000 MHz (K75)

[edit] Thunderbird (180 nm)
L1-Cache: 64 + 64 KiB (Data + Instructions)
L2-Cache: 256 KiB, fullspeed
MMX, 3DNow!
Slot A & Socket A (EV6)
Front side bus: 200 MT/s (Slot-A, B-models), 266 MT/s (C-models) (100, 133 MHz double-pumped)
VCore: 1.7 V - 1.75 V
First release: June 5, 2000
Clockrate:
Slot A: 650 - 1000 MHz
Socket A, 200 MT/s FSB (B-models): 650 - 1400 MHz
Socket A, 266 MT/s FSB (C-models): 1000 - 1400 MHz

Had to make the edit with the info before i had to hear someone say how stupid i am and i should show some proof.

It was the slot a k7 athlon however i still have one of those in a box somewhere. Really wish i had a board for it since it would make for a good file server for my network. Its either that or my semperon 1500+

 

[gOJDO]

Yes, I was wrong. It was the K7 Orion breaking the 1GHz barrier.

 

[apache_lives]

Yes, I was wrong. It was the K7 Orion breaking the 1GHz barrier.

whered all the fanboys go all of a sudden? 8)

 

[m25]

Yes, I was wrong. It was the K7 Orion breaking the 1GHz barrier.

whered all the fanboys go all of a sudden? 8)
...wait till some 4x4 reviews (already late) and other stuff come out; no matter what the results we'll see a hell of fireworks :twisted:

 

[XBGT]

:lol: :lol: :lol: I think the reason I purchased my K-III 450 was because it was sooooooo much cheaper than the equivalent Pentium chip of the time and my house has aircon so the heat was not such an issue....the case panel would always be off....lol...AWE32...with DSP Chip....mmmmmmmmmmm.....big......!

 

[TabrisDarkPeace]

K6-2 did not have level 2 cache integrated, if any was present it was on the mainboard itself, and often accessed via the much slower FSB.

K6-2+ had 128 KB level 2 cache.

K6-3 had 256 KB level 2 cache, and was good for cheap SOHO servers at the time if gaming performance was not a concern. Except it was more expensive.

All the K6-2/3 CPUs had a very large Level 1 cache though, but its set 'associativity'* was not always optimal (for time-demos, and synthetics it helped, but in real-life apps it didn't).

*(Is this even a real word ?)

All you need to know is IPC, feature set (K6-2 series lacked full SSE support, and only had 1 MMX unit from memory), and CPU cache hit rate (for each system) on a given series of CPU benchmarks.

Have you checked SiSoft SANDRA CPU charts for each CPU (They are old, but should still be listed) ?

The Intel Pentium II / Celeron (maybe even Pentium Pro) had what is jokingly referred to as a 'back side bus', and could access both the cache and FSB at the same time (aggregating their performance). Unfortunately this design was missed in the history books as most ppl were to 'dumb' back then to notice or document it.