AMD News Galore: Threadripper, EPYC, Ryzen Pro Processors, Integrated Vega Graphics For APUs, 7nm Ryzen Roadmap

[Guest]

AMD Announces Threadripper, EPYC, And Ryzen Pro Processors, Integrated Vega Graphics for APUs, and an updated roadmap to 7nm.

AMD News Galore: Threadripper, EPYC, Ryzen Pro Processors, Integrated Vega Graphics For APUs, 7nm Ryzen Roadmap : Read more

 

[bit_user]

EPYC for the data center

No. No they didn't.

Ouch. That's worse than a bad pun.

 

[bit_user]

The processors support eight memory channels per socket, for a total of 16 DDR4 channels and 32 DIMMs in a two-socket server

Ah, but the catch is that it has the memory topology of a 8-CPU system. Lots of aggregate performance to be had, but you've got to take great care in distributing your data & threads.

 

[JamesSneed]

What a fun year this is turning out to be a tech enthusiast. Kaby Lake, Ryzen, Vega, "Threadripper", Skylake-x, Kaby-Lake-x. I don't recall this much going on in one year a loooong time.

 

[rhysiam]

We'll have to see how the infinity fabric and inter-core/inter-die latency plays out with server workloads, but if AMD have been able to keep that under control then those HEDT and Server CPUs look amazing. "EPYC" is an awful name, especially for a server CPU, but it's performance that counts.

AMD also displayed EPYC with the heatspreader removed, and we spotted four 8-core Zeppelin die on a single package (MCP). These four die are glued together with AMD's Infinity Fabric.

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels). With AMD's limited resources, having a single flexible silicone die makes sense, and also makes their achievements with "zen" all the more impressive IMHO. Does this also shed light on the lower clock speeds and sometimes less than competitive IPC (particularly with gaming workloads) on Ryzen 7 & 5 CPUs? Trying to make such a scale-able design must involve compromises along the way?

My one disappointment with all this is seeing Zen 2 tied to a new process. AMD were talking up plenty of "low hanging fruit" which could be addressed in future zen architectures to raise IPC and clock speeds, which makes sense when iterating on a brand new architecture (as opposed to Intel's core architecture, where all the easy performance gains were extracted years ago). Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands, and means many of the performance/power improvement dot points are likely to come from process improvements as much as architectural refinements.

Anyway - interesting times for sure.

 

[bit_user]

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels).

Don't praise them until you see the data. If they haven't got more PCIe lanes per Zeppelin than the 20 (24, if you're stretching it) that Ryzen exposed, I think it might not be enough.

Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands,

Agreed. I sure wish they could use Samsung. I have yet to see their Glo-Fo ties do anything but weigh them down. They better be getting some sweet wafer pricing, at least.

 

[InvalidError]

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design

It isn't really that impressive, this is basically a 4S multi-CPU built into a single MCM. Same principles but higher integration.

 

[WeldonB8]

Kinda like "JAMESSNEED" said this is turning out to be an exciting year, near the end of summer last year I read somewhere 2017 will be a year to remember, and to watch out for Intel, I don't recall anything about AMD but Iv bought every component for a new rig except CPU, mobo and RAM just waiting to see what comes out lol.

 

[Johnpombrio]

One Ryzen core=Ryzen HEDT. 2 Ryzen cores=Threadripper. 4 Ryzen cores (plus one BIG interposer and a whole lot of pins)=EYPC.

 

[bit_user]

What a fun year this is turning out to be a tech enthusiast. Kaby Lake, Ryzen, Vega, "Threadripper", Skylake-x, Kaby-Lake-x.

You forgot 3D X-Point finally reaching the market.

People rip on Intel for being late and falling short of their original claims, but honestly it's the brightest persistent memory technology on the (near) horizon. And it arrives none too soon - just as ever slower 3 & 4-level cell NAND is starting to dominate. Now, we just need prices to fall down to Earth.

 

[bit_user]

One Ryzen core=Ryzen HEDT. 2 Ryzen cores=Threadripper. 4 Ryzen cores (plus one BIG interposer and a whole lot of pins)=EYPC.

Yes, if you mean dies - not "cores".

 

[rhysiam]

Don't praise them until you see the data. If they haven't got more PCIe lanes per Zeppelin than the 20 (24, if you're stretching it) that Ryzen exposed, I think it might not be enough.

On the HEDT platform, two dies would provide 40 PCIe 3.0 lanes with extra PCIe 2.0 lanes to cover SATA, networking, etc. That sounds fairly reasonable to me. It's not groundbreaking, but it's competitive at least.

On the server platform (I can't bear to use that stupid name), the press release specifically mentions 128 PCIe 3.0 lanes. On face value that's certainly competitive, though it probably requires the dual socket board. I'm guessing 16 PCIe lanes coming for each of the 8 zeppelin dies across the two sockets. It'll be very interesting to see how PCIe bandwidth and latency plays out. Inter-die and inter-socket bandwidth and latency is going to be critical for consistent performance I would have thought.

You're right to question my enthusiasm though... we absolutely need to wait for data.

It isn't really that impressive, this is basically a 4S multi-CPU built into a single MCM. Same principles but higher integration.

It just strikes me that **if** these HEDT and server CPUs compete as it looks like they **might**, then AMD have played a pretty strong hand with limited resources. With the limited R&D investment in designing and producing a single die they have produced a range of CPUs that look like they **might be** at least competitive from $140 to $3000-4000 or maybe even higher. Maybe that's not "impressive" from a technical perspective, I don't know, but it seems quite a feat to me considering the resources they had to work with. Obviously we need to wait for detailed reviews to see if they perform as expected. It's not like AMD have a stellar track record when it comes to trouble-free product launches, so it will be interesting to watch.

 

[FritzEiv]

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels).

Don't praise them until you see the data. If they haven't got more PCIe lanes per Zeppelin than the 20 (24, if you're stretching it) that Ryzen exposed, I think it might not be enough.

Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands,

Agreed. I sure wish they could use Samsung. I have yet to see their Glo-Fo ties do anything but weigh them down. They better be getting some sweet wafer pricing, at least.

Toward the end as I was packing up -- I had to duck out to catch a flight back home -- I heard Lisa Su say something about Glo-Fo AND TSMC.

Also, jumping on @JamesSneed's bandwagon, not just those, and not just also 3DXpoint, but also Volta.

 

[bit_user]

Don't praise them until you see the data. If they haven't got more PCIe lanes per Zeppelin than the 20 (24, if you're stretching it) that Ryzen exposed, I think it might not be enough.

On the HEDT platform, two dies would provide 40 PCIe 3.0 lanes with extra PCIe 2.0 lanes to cover SATA, networking, etc. That sounds fairly reasonable to me. It's not groundbreaking, but it's competitive at least.

On the server platform (I can't bear to use that stupid name), the press release specifically mentions 128 PCIe 3.0 lanes. On face value that's certainly competitive, though it probably requires the dual socket board.

Your original point was good. But now you're just looking at raw numbers and assuming they're comparable to Intel's. I'm saying they're not. These CPUs are NUMA on the inside. Their topology is fundamentally different than big Intel server CPUs.

Also, you're making assumptions - like that there are another 8 lanes/die hiding inside there. We don't know that. They could be routing the 24 lanes/die through a big PCIe switch, to get 128 lanes from the 96.

Anyway, so it's 128 lanes per Epyc CPU. However, if you use two CPUs, then 64 lanes get used for inter-CPU communication. So, the total stays at 128 lanes for peripherals, even in a dual-CPU system.

 

[ravewulf]

I've definitely warmed up to the Ryzen name, but I'm not so sure about EPYC. Hopefully data center/server customers are willing to either go with it or overlook the name so AMD can get back some market share. The news and product specs are definitely exciting in any case.

 

[rhysiam]

Your original point was good. But now you're just looking at raw numbers and assuming they're comparable to Intel's. I'm saying they're not. These CPUs are NUMA on the inside. Their topology is fundamentally different than big Intel server CPUs.

Also, you're making assumptions - like that there are another 8 lanes/die hiding inside there. We don't know that. They could be routing the 24 lanes/die through a big PCIe switch, to get 128 lanes from the 96.

Anyway, so it's 128 lanes per Epyc CPU. However, if you use two CPUs, then 64 lanes get used for inter-CPU communication. So, the total stays at 128 lanes for peripherals, even in a dual-CPU system.

No assumptions - just speculation. Perhaps I didn't make that as clear as I intended.

 

[redgarl]

What I am the most impress with is their mobile strategy. Literally, AMD wants to ban Nvidia from the low to mid gaming laptop market. It's huge and there is no way a 1060M or a 1050TI M makes sense anymore. You cannot compete with a single chip if you have two when it comes to power efficiency. And the size of laptop to. You can put everything on a single PCB.

And Epyc 16 core...? Even Skylake X is rumored at 12-16 cores.

And big Vega at 12.5 TFLOPS.

AMD is back as an important contender and their products are about to get on the shelf which is impressive. I guess the investors are looking like dumbasses now after selling their stock. It's almost back to what it was.

 

[JamesSneed]

I've definitely warmed up to the Ryzen name, but I'm not so sure about EPYC. Hopefully data center/server customers are willing to either go with it or overlook the name so AMD can get back some market share. The news and product specs are definitely exciting in any case.

It does seem a bit childish for a data center name especially spoken as "EPIC". I think they should come up with better names simply for marketing purposes. How about another childish one Rryptonite.

 

[InvalidError]

And Epyc 16 core...? Even Skylake X is rumored at 12-16 cores.

No, Ryzen HEDT/19xxX is 10-16 cores using two dies on its MCM. EPYC is up to 32 cores per MCM using four dies and 64 cores per system in a dual socket configuration.

 

[Oranthal]

EPYC for the data center

No. No they didn't.

Ouch. That's worse than a bad pun.

All the names are meme city

 

[Oranthal]

We'll have to see how the infinity fabric and inter-core/inter-die latency plays out with server workloads, but if AMD have been able to keep that under control then those HEDT and Server CPUs look amazing. "EPYC" is an awful name, especially for a server CPU, but it's performance that counts.

AMD also displayed EPYC with the heatspreader removed, and we spotted four 8-core Zeppelin die on a single package (MCP). These four die are glued together with AMD's Infinity Fabric.

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels). With AMD's limited resources, having a single flexible silicone die makes sense, and also makes their achievements with "zen" all the more impressive IMHO. Does this also shed light on the lower clock speeds and sometimes less than competitive IPC (particularly with gaming workloads) on Ryzen 7 & 5 CPUs? Trying to make such a scale-able design must involve compromises along the way?

My one disappointment with all this is seeing Zen 2 tied to a new process. AMD were talking up plenty of "low hanging fruit" which could be addressed in future zen architectures to raise IPC and clock speeds, which makes sense when iterating on a brand new architecture (as opposed to Intel's core architecture, where all the easy performance gains were extracted years ago). Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands, and means many of the performance/power improvement dot points are likely to come from process improvements as much as architectural refinements.

Anyway - interesting times for sure.

Zen 2 is 7nm , Zen + is the low hanging fruit coming next year

 

[rhysiam]

Zen 2 is 7nm , Zen + is the low hanging fruit coming next year

Source? If true, it's strange that AMD didn't put that up on their road-map.

 

[bloodroses]

AMD is certainly going for some edgy names there (Epyc, threadripper). I wonder what they'll end up calling their APU since Raven Ridge is the code name?

 

[InvalidError]

Zen 2 is 7nm , Zen + is the low hanging fruit coming next year

Source? If true, it's strange that AMD didn't put that up on their road-map.

AFAIK, the Zen+ name is something that surfaced back when we didn't know what the next Zen would be called, not an official name for anything. That said, with Zen 2 in 2019, AMD will still need something to launch in 2018 and it would make sense to have a Zen refresh of some sort.

 

[Oranthal]

Zen 2 is 7nm , Zen + is the low hanging fruit coming next year

Source? If true, it's strange that AMD didn't put that up on their road-map.

AFAIK, the Zen+ name is something that surfaced back when we didn't know what the next Zen would be called, not an official name for anything. That said, with Zen 2 in 2019, AMD will still need something to launch in 2018 and it would make sense to have a Zen refresh of some sort.

Correct they gave no name but they verbally did state a 2018 refresh before zen 2. Slide three they list 14nm+ below 14nm aka the refresh. They also verbally mentioned it.. Link to slide deck below.

http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-analystday