AMD News Galore: Threadripper, EPYC, Ryzen Pro Processors, Integrated Vega Graphics For APUs, 7nm Ryzen Roadmap

[Giroro]

I'm hoping Ryzen Pro is a new die with some tweaks to improve some of Ryzen's deficiencies.

 

[Giroro]

At least it's not Threydryppyr.

 

[jimmysmitty]

We'll have to see how the infinity fabric and inter-core/inter-die latency plays out with server workloads, but if AMD have been able to keep that under control then those HEDT and Server CPUs look amazing. "EPYC" is an awful name, especially for a server CPU, but it's performance that counts.

AMD also displayed EPYC with the heatspreader removed, and we spotted four 8-core Zeppelin die on a single package (MCP). These four die are glued together with AMD's Infinity Fabric.

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels). With AMD's limited resources, having a single flexible silicone die makes sense, and also makes their achievements with "zen" all the more impressive IMHO. Does this also shed light on the lower clock speeds and sometimes less than competitive IPC (particularly with gaming workloads) on Ryzen 7 & 5 CPUs? Trying to make such a scale-able design must involve compromises along the way?

My one disappointment with all this is seeing Zen 2 tied to a new process. AMD were talking up plenty of "low hanging fruit" which could be addressed in future zen architectures to raise IPC and clock speeds, which makes sense when iterating on a brand new architecture (as opposed to Intel's core architecture, where all the easy performance gains were extracted years ago). Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands, and means many of the performance/power improvement dot points are likely to come from process improvements as much as architectural refinements.

Anyway - interesting times for sure.

I always laugh when AMD uses a MCM approach after basically lambasting Intels Core 2 Quad doing the same thing.

Guess we will see how it works out.

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)? That's some impressive scaling AMD have managed if they can use a single die design, with multiple package arrangements (1, 2 or 4 dies on package), to scale from a mid range consumer CPU (Ryzen 5 1400), through HEDT (16 core 32 thread), all the way up to a premium dual socket compatible server CPU (32 core, 64 thread, 8 RAM channels).

Don't praise them until you see the data. If they haven't got more PCIe lanes per Zeppelin than the 20 (24, if you're stretching it) that Ryzen exposed, I think it might not be enough.

Tying Zen2 to Glo-Fo's 7nm process put the timelines largely out of AMD's hands,

Agreed. I sure wish they could use Samsung. I have yet to see their Glo-Fo ties do anything but weigh them down. They better be getting some sweet wafer pricing, at least.

What do you mean? Glo-Flos 14nm is Samsungs 14nm LPP process. Glo-Flo has done very little process research. And it has not done a damn thing for them either.

The 7nm is their own but I am not sure it will come as fast as they want.

 

[mavikt]

All of a sudden I can't get "EPYC failure" of my mind... /s

 

[rhysiam]

Correct they gave no name but they verbally did state a 2018 refresh before zen 2. Slide three they list 14nm+ below 14nm aka the refresh. They also verbally mentioned it.. Link to slide deck below.

http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-analystday

That's somewhat encouraging.

Rumours have Coffee Lake launching with a 6 core i7 on the mainstream platform.That could well (speculating here) mean hyperthreaded i5s. *If* that turns out to be true and *if* Intel stick with the traditional i7/i5 prices (both are massive "ifs" at this point), then the entire first gen Ryzen lineup starts to look a whole lot less attractive. A (hypothetical) 4C8T i5 would get very close to the top end Ryzen 5 lineup in multithreaded tasks while maintaining Intel's single threaded and gaming advantages. A (hypothetical) 6C12T i7 would do the same to the entire Ryzen 7 lineup.

AMD have a really competitive CPU lineup right now, but Intel is hardly going to sit still. Obviously it's all "ifs" and speculation at this point, but right now AMD's prime selling point is cores/threads per dollar. If Intel attack them on that front then AMD will need to answer with bumps in IPC or clock speed (probably both) to stay competitive in the $150 - $500 market. If Ryzen 2 is tied to 7nm and likely 2019, I think there will be quite a lot riding on a Zen+/Zen1.5 lineup on 14nm.

 

[alextheblue]

And Epyc 16 core...? Even Skylake X is rumored at 12-16 cores.

No, Ryzen HEDT/19xxX is 10-16 cores using two dies on its MCM. EPYC is up to 32 cores per MCM using four dies and 64 cores per system in a dual socket configuration.

You mean 12-16? Or are you anticipating lopsided configs, such as 4:6?

 

[rhysiam]

And Epyc 16 core...? Even Skylake X is rumored at 12-16 cores.

No, Ryzen HEDT/19xxX is 10-16 cores using two dies on its MCM. EPYC is up to 32 cores per MCM using four dies and 64 cores per system in a dual socket configuration.

You mean 12-16? Or are you anticipating lopsided configs, such as 4:6?

There was a pretty widely circulated rumour that identified 10-16 cores with specific product names. Here's one of the (many) sites that reported on it: http://hexus.net/tech/news/cpu/105724-amd-ryzen-9-threadripper-cpus-rumoured-offer-16c32t/
Obviously all rumours at this point, but the 10 core is mentioned.

 

[alextheblue]

So are these literally identical dies to the ones we see in current Ryzen consumer products (Ryzen 7 etc)?

It seems likely that there are some slight differences. EPYC has 32 PCIe 3.0 lanes per die, vs Ryzen consumer's 20 + some 2.0 lanes. EPYC will work in dual and single socket configs, and from what I've read has very competitive memory bandwidth in the 1S/2S world. Should be very interesting to see if they can claw back some market share and build up a little cash for future R&D.

 

[InvalidError]

You mean 12-16? Or are you anticipating lopsided configs, such as 4:6?

AMD could very well do 2+3 + 2+3, which is what I think is going to be the 10-core (R9-1955) config. Since each die has its own two channel memory controller, having an uneven core count distribution across dies could cause significant performance scaling issues.

BTW, there is also a 14 cores model (R9-1977), which can only be achieved by doing 4+3 + 4+3, so AMD is indeed planning to release chips with an uneven number of enabled cores per CCX.

BTW2: notice how the model numbers seem to be 19 followed by the number of active cores per die?

 

[Karadjgne]

All this supposition. Yet here's what I see. AMD is making their own version of the 2011-3 and Xeon packages. (it's about time too). I see that nerd from TV announcing 95% of the world's Internet is powered by Intel. Well no wonder when AMD's best offering was an FX. What I see is a brand new line of AMD cpus that'll not only hold its own vrs comparable Intel, but actually beat them in many scenarios not gaming oriented. So EPYC is AMD's answer to the Xeon. Kudos. Now all AMD needs to do is actually fix their new cpus (memory speeds in particular come to mind) before the public starts comparing Ryzen to its other vastly hyped release, the Zambezi

 

[bit_user]

EPYC has 32 PCIe 3.0 lanes per die

According to whom?

 

[InvalidError]

EPYC has 32 PCIe 3.0 lanes per die

According to whom?

If you look at the Zeppelin die picture from AMD's press conference, you can see 34 HSIO macros on it split into six groups of four and five pairs. Two clusters of 16 lanes are at opposite corners of the chip and the 5th pair is in the middle of the MCM fabric IOs.

 

[bit_user]

If you look at the Zeppelin die picture from AMD's press conference, you can see 34 HSIO macros on it split into six groups of four and five pairs. Two clusters of 16 lanes are at opposite corners of the chip and the 5th pair is in the middle of the MCM fabric IOs.

That's some good eyeballs. Thanks!

 

[InvalidError]

That's some good eyeballs. Thanks!

When I first looked at the die picture and the R7's specs, the amount of apparent wasted space made no sense. Now that we know AMD is using the same die all the way up to Naples, it is more understandable. Hopefully AMD will sell enough HEDT and server/workstation chips to make that gamble pay off. I's imagine 32C64T (quad-zeppelin) should sell quite well for ~5X the cost of an R7-1800X.

 

[steve_196]

I hope that all this cpu fun will be on am4 or backwards compatible

 

[Karadjgne]

Doubtful, pin counts will be way different if nothing else, it's going to be like lga1151 vrs lga 2011-3 with those amounts of pcie lanes among others. The Ryzen 2 maybe, haven't looked, but amd has a tendency to really beat a dead horse with sockets and the original Zen+ was supposed to be the same socket as Zen.

 

[JamesSneed]

I hope that all this cpu fun will be on am4 or backwards compatible

The HEDT Ryzen aka "Threadripper" line is not on the AM4 socket it will slot into a SP3r2 4094-pin socket. They are following Intel here and bringing server chips down into the HEDT line which is great for workstations. Why you get quad channel memory etc. I see no issue with having a different socket in this line. Hopefully the next generation or two will still slot into AM4 or SP3r2 so if you pick one direction you should have an upgrade path.

 

[Oranthal]

Correct they gave no name but they verbally did state a 2018 refresh before zen 2. Slide three they list 14nm+ below 14nm aka the refresh. They also verbally mentioned it.. Link to slide deck below.

http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-analystday

That's somewhat encouraging.

Rumours have Coffee Lake launching with a 6 core i7 on the mainstream platform.That could well (speculating here) mean hyperthreaded i5s. *If* that turns out to be true and *if* Intel stick with the traditional i7/i5 prices (both are massive "ifs" at this point), then the entire first gen Ryzen lineup starts to look a whole lot less attractive. A (hypothetical) 4C8T i5 would get very close to the top end Ryzen 5 lineup in multithreaded tasks while maintaining Intel's single threaded and gaming advantages. A (hypothetical) 6C12T i7 would do the same to the entire Ryzen 7 lineup.

AMD have a really competitive CPU lineup right now, but Intel is hardly going to sit still. Obviously it's all "ifs" and speculation at this point, but right now AMD's prime selling point is cores/threads per dollar. If Intel attack them on that front then AMD will need to answer with bumps in IPC or clock speed (probably both) to stay competitive in the $150 - $500 market. If Ryzen 2 is tied to 7nm and likely 2019, I think there will be quite a lot riding on a Zen+/Zen1.5 lineup on 14nm.

I have zero faith Intel will release any of that before mid 2018 at the earliest. I also have no faith that the new platform will be priced near a R5 AM4 setup. AMD has said publicly a 10-15% improvement via clock speed/ipc will come plus memory latency for gaming tweaks. Bios improvements will trickle out all year as well. Intel will probably drop a big hammer I just don't think it will come that soon. Intel 10nm has been so heavily delayed I wonder if it will ever come.

 

[JamesSneed]

Correct they gave no name but they verbally did state a 2018 refresh before zen 2. Slide three they list 14nm+ below 14nm aka the refresh. They also verbally mentioned it.. Link to slide deck below.

http://ir.amd.com/phoenix.zhtml?c=74093&p=irol-analystday

That's somewhat encouraging.

Rumours have Coffee Lake launching with a 6 core i7 on the mainstream platform.That could well (speculating here) mean hyperthreaded i5s. *If* that turns out to be true and *if* Intel stick with the traditional i7/i5 prices (both are massive "ifs" at this point), then the entire first gen Ryzen lineup starts to look a whole lot less attractive. A (hypothetical) 4C8T i5 would get very close to the top end Ryzen 5 lineup in multithreaded tasks while maintaining Intel's single threaded and gaming advantages. A (hypothetical) 6C12T i7 would do the same to the entire Ryzen 7 lineup.

AMD have a really competitive CPU lineup right now, but Intel is hardly going to sit still. Obviously it's all "ifs" and speculation at this point, but right now AMD's prime selling point is cores/threads per dollar. If Intel attack them on that front then AMD will need to answer with bumps in IPC or clock speed (probably both) to stay competitive in the $150 - $500 market. If Ryzen 2 is tied to 7nm and likely 2019, I think there will be quite a lot riding on a Zen+/Zen1.5 lineup on 14nm.

I have zero faith Intel will release any of that before mid 2018 at the earliest. I also have no faith that the new platform will be priced near a R5 AM4 setup. AMD has said publicly a 10-15% improvement via clock speed/ipc will come plus memory latency for gaming tweaks. Bios improvements will trickle out all year as well. Intel will probably drop a big hammer I just don't think it will come that soon. Intel 10nm has been so heavily delayed I wonder if it will ever come.

I suspect Intel is going to move up Icelake from a 2019 release to a late 2018 release. Icelake is there big hammer. Intel is pretty smart and this is the smart move to get the new micro architecture out sooner now that there is competition. When AMD comes out with Ryzen+ it assuredly will clock a bit better and have at least a slight IPC improvement which should land AMD really close to Kaby Lake but with more cores.

 

[aldaia]

In relation to EPYC performance looks like Dropbox is apparently happy, with Akhil Gupta, vice president of infrastructure at Dropbox, noting that they are impressed with the initial results of their single-socket EPYC box. “The combination of core performance, memory bandwidth, and I/O support make EPYC a unique offering,” he said. “We look forward to continuing to evaluate EPYC as an option for our infrastructure.”

 

[alextheblue]

You mean 12-16? Or are you anticipating lopsided configs, such as 4:6?

AMD could very well do 2+3 + 2+3, which is what I think is going to be the 10-core (R9-1955) config. Since each die has its own two channel memory controller, having an uneven core count distribution across dies could cause significant performance scaling issues.

BTW, there is also a 14 cores model (R9-1977), which can only be achieved by doing 4+3 + 4+3, so AMD is indeed planning to release chips with an uneven number of enabled cores per CCX.

BTW2: notice how the model numbers seem to be 19 followed by the number of active cores per die?

Yeah I didn't mean to imply it wasn't going to happen, I just hadn't heard about it yet. That makes sense - having a different number of cores active per CCX could also have a performance impact, but not as much as differing number per die. Either way, in the server world it probably will not be as big of a deal, as they are used to distributing their load across multiple processors with restrictive layouts. In the PC realm even a lot of multi-threaded workloads aren't perfectly ideal for Ryzen without modification - for example, some of the recent game patches.

Anyway it will be very interesting to see how this does in the HEDT and server market that craves cores and bandwidth. If they sell well AMD will be well on their way to recovery. Next up, mobile APUs with graphics performance rivalling entry-mid level discrete graphics?

 

[kyotokid]

....unless Epyc/Naples CPUS are really really fast on their own, the fact they are designed to specifically interact with AMD GPUs makes me wonder how good they'd be for Iray and Octane since both engines require Nvidia CUDA for GPU based rendering.

 

[Karadjgne]

As massively complex as these new cpus are as compared to older cpus, as much as they are packing into the die just to enable that amount of pcie lanes, clock speeds, mc, everything, I find it a little bit of too much to design any of those cpus around performance bonuses for amd gpus. That's gotta be either a coincidence or a play on words or something. It'd be far easier to have designed the 500 series to be better compatible with the new cpus, than the other way around.

 

[kyotokid]

As massively complex as these new cpus are as compared to older cpus, as much as they are packing into the die just to enable that amount of pcie lanes, clock speeds, mc, everything, I find it a little bit of too much to design any of those cpus around performance bonuses for amd gpus. That's gotta be either a coincidence or a play on words or something. It'd be far easier to have designed the 500 series to be better compatible with the new cpus, than the other way around.

...makes much better sense as then they would be compatible with either brand of GPU and thus maybe net more sales.

A workstation with Dual Epycs and 1 TB of 16 channel physical memory would be pretty shredding with biased raytrace render engines that don't support GPU rendering like Vue, Carrara, and Renderman/3DL. It could probably even knock out a big scene in Iray in a more reasonable amount of time.

 

[Karadjgne]

Exactly my point, in a round about way. Tailoring a cpu specifically for just amd gpus seems pointless, ppl pushing the kind of power you describe would also likely be using that DGX-1 tesla or similar if gpu rendering as firepros don't have anything quite as close. So it'd have to be a play on wording that all that power with all those pcie lanes etc will actually be able to make better use of amd gpus, vrs designing a cpu to take on the Xeon Reign that cuts out a very large portion of the work base.