[citation][nom]silverblue[/nom]Ivy Bridge's graphics will be a large improvement on before; enough to bring them close to, if not equal to, the higher end of the Llanos we have now.[/citation]
I seriously doubt that Ivy Bridge would come close; the HD 4000's main improvement is that it goes from 12 to 16, and it adds DX11 support; the latter was the source of some possible media claims of "catching up." Of course, almost all enthusiasts know that simply adding support for the latest DX hardly doesn anything; otherwise the HD 4000 would be as good as a GTX 590 or 6990. This DX support, however, accounts for most of the "bulking up" here; after all, Intel spent the (likely wasted) resources to put in full hardware tessellation support.
All told, even though the HD graphics clock higher than other GPUs, it hardly makes up for having only 16 shaders. Since they're vector units not superscalar, we have to compare the quantity to GeForce cards... And even still, 16 is an abysmally low number; we're talking something like the GeForce 8500GT. (as the only GF card that had 16 shaders without also having a 64-bit memory interface) And yes, the clock speed difference is a bit mitigated here, since nVidia clocks their shaders higher than the core clock; 900 MHz is within the range for the HD 4000, and a bit above the middle of the range.
An 8500GT isn't a match for even a low-end Radeon 6000-series card. It doesn't even come close. So again, Ivy Bridge's graphics will keep up the pace with Sandy Bridge, and remain a joke.
[citation][nom]silverblue[/nom]The only way they're going to reduce transistor count is to cut the L3 cache size or redesign it completely so it doesn't require so many transistors, though I'm not sure as to how that would be achieved.[/citation]
Well, more efficient (read: simpler) designs could be figured out to accomplish the same results in hardware. As I'd mentioned, AMD had done it before when they transitioned from R600/RV670 to RV770, where they managed to make each stream processor take up less die space without using a die shrink, purely by re-designing them.
Also, +1 for the careful thought and linkage. I hadn't had any time to pay attention to the Bulldozer die count controversy, so it's good to have that cleared up.[citation][nom]silverblue[/nom]MasoNobody has refuted the 213m transistors required for a module. Do you really think that 8MB of L3 cache, the IMC, processor interconnects etc. make up the other 348M[/citation]
Of course, the extra has to be even more, since 1MB of cache requires slightly more than 50M transistors. (each SRAM cell uses 6 transistors, vs. DRAM cells which typically use one transistor and one capacitor)
on other hands , well intel`s deep pockets prevails even in consumer PC builders puttin crappy I3 and crapy intel HD graphics instead of AMD`s Llano APU.
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